Interface Descriptions; The Pci Interface; The Scsi Interface - LSI LSI8751SP User Manual

1.3 Interface Descriptions

1.3.1 The PCI Interface

1.3.2 The SCSI Interface

This section provides a more detailed explanation about the PCI
Interface, the SCSI Interface, and Ultra SCSI.
PCI is a high-speed standard local bus for interfacing a number of I/O
components to the processor and memory subsystems in a high end PC.
The PCI functionality for the LSI8751SP is contained within the
LSI53C875J PCI to SCSI I/O Processor chip. The LSI53C875J connects
directly to the PCI bus and generates timing protocol in compliance with
the PCI Local Bus Specification Revision 2.0 standard.
The PCI interface operates as a 32-bit DMA bus master. The connection
is made through edge connector J1 (see
definitions and pin numbers conform to the PCI Local Bus Specification
Revision 2.0 standard. The LSI8751SP conforms to the PCI universal
signaling environment for a 5 V or 3.3 V PCI bus.
The SCSI functionality for the LSI8751SP is contained within the
LSI53C875J PCI-SCSI I/O Processor chip. The LSI53C875J connects
directly to the SCSI bus and generates timing and protocol in compliance
with the SCSI standard.
The SCSI interface on the LSI8751SP operates as 8-bit or 16-bit,
synchronous or asynchronous, SE bus, and supports Ultra SCSI
protocols and 16-bit arbitration. The interface is made through two (and
only two) of the connectors J2, J3,s and J4. These connectors are shown
in Figure 2.1. Connector J2 is a 68-pin high density right angle
receptacle. Connector J3 is a shielded 68-pin high density right angle
receptacle that protrudes through the back panel bracket. Connector J4
is a 50-pin low density vertical shrouded pin header.
SE SCSI active termination is provided for the LSI8751SP. Termination
is automatically enabled when only one of the connectors J2, J3, or J4
is used. The LSI8751SP supplies SCSI bus TERMPWR through a
blocking diode and a self-resetting 1.5 A short circuit protection device.
Termination is disabled when two connectors are used.
Interface Descriptions
Figure 2.1). The signal
1-3