Jumper Settings; Table 5. Jumper Settings - Cirrus Logic CDB43L22 Manual

6. JUMPER SETTINGS

JMP LABEL
J31 VL
J36 VA_HP
J25 VA
J28 VD
J52 VL
J47 +VA_HP
J74 VA
J53 VD
J48 VP
J13
[No Label]
J14
J16
[No Label]
J17
J11
[No Label]
J12
J20
[No Label]
J23
J15 MONO
J19 MONO
J3 HP B LOAD
J9 HP A LOAD
J1 LEFT CH
J2 RIGHT CH
J22 HP DETECT
J34 Board Power
J5 VP
18
PURPOSE
Selects source of voltage for the
VL supply
Selects source of voltage for the
VA_HP supply
Selects source of voltage for the
VA supply
Selects source of voltage for the
VD supply
Current Measurement
Current measurement
Applies a filtered or a non-filtered
version of the SPKA- signal to J60
Applies a filtered or a non-filtered
version of the SPKA+ signal to J59
Applies a filtered or a non-filtered
version of the SPKB- signal to
J101
Applies a filtered or a non-filtered
version of the SPKA- signal to J99
Applies a short between SPKOUT
A+ and A-. (Used only after
MONO function is enabled in the
CS43L22)
Applies a short between SPKOUT
B+ and B-. (Used only after
MONO function is enabled in the
CS43L22)
Selects 32 or 16 Ω load for
HP/LINE_OUTB (DAC out)
Selects 32 or 16 Ω load for
HP/LINE_OUTA (DAC out)
Selects between a filtered or non
filtered version of the
HP/LINE_OUTA signal.
Selects between a filtered or non
filtered version of the
HP/LINE_OUTB signal.
Selects the control source for the
SPKR/HP pin
Selects either USB or External
+5 V power for the board
Selects either External or Battery
power for VP and for the buck reg-
ulators that powers VA, VA_HP
and VD

Table 5. Jumper Settings

POSITION FUNCTION SELECTED
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator.
+3.3V Voltage source is +3.3 V regulator.
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator.
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator.
*+1.8V Voltage source is +1.8 V regulator.
+2.5V Voltage source is +2.5 V regulator.
1 Ω series resistor is shorted.
*SHUNTED
1 Ω series resistor in power supply path.
OPEN
*SHUNTED VP supply to CS43L22 is selected.
*1 - 2 SPKOUTA- output routed to J60.
2 - 3 SPKOUTA- output not routed to J60.
*1 - 2 SPKOUTA+ output routed to J59.
2 - 3 SPKOUTA+ output not routed to J59.
*1 - 2 SPKOUTB- output routed to J101.
2 - 3 SPKOUTB- output not routed to J101.
*1 - 2 SPKOUTB+ output routed to J99.
2 - 3 SPKOUTB+ output not routed to J99.
Channel A+ and A- to J59 and J60 respec-
*OPEN
tively.
Channel + to J59 and J60 respectively.
SHUNTED
Channel B+ and B- to J99 and J101 respec-
*OPEN
tively.
SHUNTED Channel - to J99 and J101 respectively.
16 Ω load selected.
1 - 2
32 Ω load selected.
2 - 3
16 Ω load selected.
1 - 2
32 Ω load selected.
2 - 3
1 - 2 Non-filtered HP/LINE_OUTA to HP/Line Jack.
Filtered HP/LINE_OUTA to HP/Line Jack.
*2 - 3
1 - 2 Non-filtered HP/LINE_OUTA to HP/Line Jack.
Filtered HP/LINE_OUTA to HP/Line Jack.
*2 - 3
1 - 2 FPGA.
*2 - 3 HP Jack.
1 - 2 External +5 V power.
USB generated +5 V power. (USB hub must be
*2 - 3
capable of greater than 300 mA)
*1 - 2 External from J35.
Battery from BT1-BT3 (bottom side)
2 - 3
CDB43L22
DS792DB1