Table 2. Jumper/Switch Settings - Cirrus Logic CDB4271 Instruction Manual

JUMPER /
SWITCH
M/S[1:0] Subclock Master/Slave Select
(S1)
MCLK[1:0] Master Clock Source Select
(S1)
Header/8416 CS4271 SDIN Source Select
(S1)
Coaxial/ Optical or Coaxial S/PDIF
Optical
(S1)
I2S/LJ Digital Interface Format Select
(S1)
128/256 Master Clock Speed Select
(S1)
M[1:0] CS4271 Speed Mode Select
(S1)
J11, J19 Selects LED or Mute Circuit for
AOUTA, AOUTB
J10 Selects source of voltage for
the VA supply
J9 Selects source of voltage for
the VD supply
J8 Selects source of voltage for
the VL supplies
J13, J14, Selects DAC Output Filter
J15, J20,
J21, J22
10
PURPOSE
Input Select

Table 2. Jumper/Switch Settings

POSITION
*00 CS4271 is Master
01 CS8416 is Master
10 CS8406 is Master
11 PCM Header, J26, is Master
*00 CS8416 Provides MCLK
01 CS4271 Provides MCLK
10 PCM Header, J26, Provides MCLK
11 PCM Header, J26, Provides MCLK
*0 CS8416 Provides SDIIN
1 PCM Header, J26, Provides SDIN
*0 Optical Input
1 Coaxial Input
*0 Left Justified, 24-bit
2
1 I S, 24-Bit
*0 256*Fs
1 128*Fs
00 Single-Speed Mode, with De-emphasis
*01 Single-Speed Mode, w/out De-emphasis
10 Double-Speed Mode
11 Quad-Speed Mode
1 Mute Circuit Affects Analog Output
*2 Mute Circuit Disconnected (LED displays
xMUTEC status)
*+5V Voltage source is J1, +5.0 V binding post
ADJ Voltage source is J5, VA binding post
*+5V Voltage source is J1, +5V binding post
+3.3V Voltage source is +3.3 V regulator
ADJ Voltage source is J3, VD binding post
*+5V Voltage source is J1, +5V binding post
+3.3V Voltage source is +3.3 V regulator
ADJ Voltage source is J2, VL binding post
*1 Selects standard 2-pole filter
2 Inserts instrumentation-amp and resistor
divider.
CDB4271
FUNCTION SELECTED
*Default factory settings