Sony MFS-2000-C Installation Manual page 31

<LED>
D204, D208 (A-3) : + + + + + 1.5 V-1, 2
+1.5 V power supply status indication.
Lit when the +1.5 V-1 and 2 power is supplied respectively.
D304, D308 (A-3) : + + + + + 2.5 V-1, 2
+2.5 V power supply status indication.
Lit when the +2.5 V-1 and 2 power is supplied respectively.
D401 (A-2) : + + + + + 12 V
+12 V power supply status indication.
Lit when the +12 V power is supplied.
If this LED does not light, the fuse may have blown.
D409 (A-2) : + + + + + 3.3 V
+3.3 V power supply status indication.
Lit when the +3.3 V power is supplied.
D2601 (A-6) : PLL UNLOCK
Indicates lock/unlock of the PLL (Phase Locked Loop) in
the FPGA.
If this LED lit, the PLL can possibly be unlocked.
D2602 (A-6) : CONFIG. ERROR
Indicates the configuration error of the FPGA.
If this LED lit, the FPGA can possibly be working incor-
rectly.
D2603, D2604, D2605 (A-6) : C2, C1 and C0 status
LED
Indicates the status of CPU on the circuit board.
D3501 (A-4) : CCR EXT
Lit when the CC-95 board is inserted.
D3801 (A-5) : FM_DATA ACT status LED
FM_DATA Ethernet communication status indication.
Lit while the data transmission or reception is in progress.
D3802 (A-5) : FM_DATA 100 status LED
FM_DATA Ethernet communication speed status indica-
tion.
Lit : 100 Mb/s
Not lit : 10 Mb/s
MFS-2000 IM
<Switch>
S401 (A-5) : MY-CPU reset switch
Pressing this switch initializes the CPU on the MY-112
board.
S3601 (A-6) : Monitor reset switch
This is a reset switch used in maintaining through the
terminal pin.
<Slit land>
SL1 (A-4), SL2 (H-5) and SL3 (A-5) : JTAG chain
switching
They are the slit lands that are used to switch the JTAG
chains. Connect these slit lands to open or to close them so
that the following statuses can be obtained.
SL1 SL2 SL3
short open open
open short short
<LED on the CPU-DR module>
Refer to < LED on the CPU-DR module > in "1. CA-54
board".
<Switch on the CPU-DR module>
Refer to < Switch on the CPU-DR module > in "1. CA-54
board".
<LED on the CPU-DT module>
Refer to <LED on the CPU-DT module> in "1. CA-54
board".
<Switch on the CPU-DT module>
Refer to <Switch on the CPU-DT module> in "1. CA-54
board".
Status
The chain of CPLD only is
established.
All of the JTAG devices are
connected in chain.
2-21