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\ . ' .
word length is fIxed at 8 and the number of stop bits
is
fIxed at 2. Table I on the schematic shows
that the parity (ON or OFF) and even or odd parity are set through terminals U and V of external
connector A6AI WI 11. These are also set by connecting the appropriate terminals to common
ground. The unconnected terminals will have +SV connected through UI. These terminals also
connect to tri-state buffer Ul2 and are strobed on to the data bus (and to PI and EPE) at the ap-
propriate time by the strobe signal out ofX2 (pin 4) of decoder U19.
The receiver number for remote addressing is selected by connecting the appropriate ter-
minals
K, L, M,
N, P, R, S, T of connector A6AI
WlJ
I (See Table I on schematic) to common. 'This·
setting through tri-s.tate buffers UII and U13B and Pull-up resistors UIO and UI is strobed onto the
data bus, for readout by the microprocessor, by the strobe from Xl (pin 3) of decoder U19:
Figure 4-23 is a block diagram of the receive station of the UART. When data is received
from the remote controller, it comes through the external connector A6AIW1Jl to Receiver U2.
Receiver U2 yields signals that are compatible to the Receiver circuits of the UART (U9) through
its RRI input (pin 20). The UART receiver section converts the incoming serial data stream from
the remote controller to 8-bit parallel words and places them on the microcomputer bus (PBO
through PB7) through outputs RB RI through RBR8. The serial format, as described previously,
is an II-bit word containing a start bit, a 7-bit ASCII code, a parity bit followed by two stop bits.
Instruction word codes are also described in Section III. When data is available from the remote
controller, an interrupt request is made by asserting the DR output, indicating data
is
available
to the microcomputer. The DR output will go through gate U8A, if not inhibited by computer
outputs 00 and
a
1
(microcomputer not accepting these interrupts), and then through gate U8B, at
the correcttime (ROMC inputs through UI7A, U6C, UI6B-D, and UI7B) to drive flip-flop UI6A.
The outputs of this flip-flop drive one of the two inputs to each of gates UI SB and UI SC. The other
input to these gates
is
the inverted
IICB
signal from the microcomputer. If the CPU
is
currently
blocking, thus ignoring interrupt requests,
IICB
will be high. Under this condition UI SB and C
gates are inhibited. When
IICB
is not high (microcomputer accepting interrupts), gates UI SB and C
are enabled. The output from UlSB, through switch UI4B, sends the lINT REQ to the micro-
computer (through pin 27 of PI) to initiate an interrupt. The microprocessor will orderly stop its
normal Receiver monitoring functions as directed by the control program (from EPROM) and start
the interrupt routine to accept data from the remote controller.
During the interrupt routine the microcomputer asserts its
IICB
output, thus not ac-
cepting any further interrupts until it has completed the routine. It will be noted that the DR out-
put from the UARTare routed through connector PI, pin 37 to the microprocessor
1/0
terminal
11. This input enables the microcomputer to determine that the interrupt request was for a
receive routine.
Figure 4-22 is a block diagram of the transmit section of the UART. When the remote
controller has requested data (status) and the transmit buffers of the UART are empty, so that it
can accept data from the microcomputer for transmission to the remote controller, the TBRE out-
put is asserted. The TBRE signal will go through gate U8A, if it is not inhibited by microcomputei
outputs 00 and
a
I (microcomputer not accepting interrupts), and then through gate U8B, at the
correct time (ROMC inputs through U17 A, U6C, U16B-D and U17B) to drive flip-flop U16A. The
outputs of these flip-flops drive one of the two inputs to each of gates Ul SB and Ul Sc. The other
input to these gates is the inverted IICB signal from the microcomputer. When the CPU in the micro-
computer is busy and ignoring interrupt requests, IICB will be high. Under this condition. Ul5B
and C gates are inhibited. When
IICB
is not high these gates (Ul SB and C) are enabled and the
IPRI
output from UlSC is output through pin 24 of
PI.
The output from UlSB, through switch
U14B, sends. the lINT REQ to the microcomputer (through pin 27 of PI) to initiate an interrupt.
The microprocessor will orderly stop its present program and start the interrupt routine to send
4-55
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