Advertisement
select A low which outputs 00 input of both U4 and US to their respective Y outputs. For U4
this is 5 MHz, for US it is I MHz. When only LK2 is linked data select A will be high and Blow
which connects both 01 inputs to their respective Y outputs (U4-5 MHz, U5-5 MHz). When both
LKI and LK2 is linked both data select A and B are held low which outputs D3 of both U4 and
US (U4-5 MHz, U5-l0MHz). As noted in this internal mode, U4 always selects the 5 MHz. It is
then routed to the phase comparator as the oscillator reference signal. The output frequency sel-
ected by US is routed through resistor R13 to buffer amplifier stages Q3 and Q2. These stages
provide for output into 50 ohms through a high pass fIlter, Ll, C6 and C7, and connector 17 on the
rear panel. The high pass filter also provides fIltering for reference frequencies applied externally
through J7 while resistors R8 and R9 provide a 50 ohm impedance to the incoming reference
frequency.
4.3.7.3
External Mode
In this mode of operation the INT/EXT switch is set to EXT and this line goes high from
the +5 volts through resistor R78. This causes transistor Ql to turn voltage regulator Ul off which
in tum turns off the internal crystal oscillator Yl. When an external oscillator is connected to con-
nector J7 on the rear panel, the input is routed through the high pass fIlter, and capacitor C8 to the
base of transistor switch Q4. The input of NOR gate U2A is now high which in turn keeps the base
of Q5 low thr9ugh diode CR3. Transistor Q4, whose base is no longer low, conducts which applies
the external reference through the TTL shaper to the same clock input of the phase comparator that
the 5 MHz reference was applied in the internal mode. The appropriate reference frequency for
application to the second clock input to the phase comparator can be selected through LKI and LK2
as in the internal mode; however, data select C is now high. Linking LKI selects 06 (10 MHz),
LK2 selects 05 (5 MHz) or both LKI and LK2 select 04
(1
MHz). The 00,01, and 02 inputs to
U5 cannot be selected when data select C is high (external mode) and no output appears on the Y
output of US.
4.3.7.4
Second Local Oscillator
Figure 4-13 shows a simplified functional block diagram of the second local oscillator.
The circuit consists maipJy of a crystal referenced, voltage controlled oscillator, a frequency doubler
output circuit and a phase lock loop includes amplifiers, an ECL to TTL buffer, three frequency
dividers (two
+
2 and a +10). reference frequency select circuit, a phase comparator and a digital to
analog converter. The three dividers are used to provide a choice of reference frequencies for internal
or external reference.
1. Phase Lock Loop. The 20 MHz oscillator frequency is kept on frequency through
a phase locked loop (See Figure 4-9). The oscillator output is routed through a divide by N circuit
that provides an oscillator reference frequency. This divided oscillator frequency is coupled to the
second clock input of a phase comparator. The phase comparator, described below, detects any
phase shift between the oscillator frequency and a reference frequency also connected to the phase
comparator. The phase comparator then changes the digital to analog converter output voltage
which is connected to the oscillator varactor and crystal. This then causes the oscillator frequency
to change. This loop action will continue until the oscillator frequency is brought into phase (same
frequency) with the reference frequency.
2. Voltage Controlled Oscillator. The 20 MHz oscillator consists of ECL OR gate U210,
20 MHz crystal Y2, varactor CR4, resistors R47. R48, R49 and R50 and capacitors C34 through
C38. Oscillation frequency is derived from the parallel combination of crystal Y2 in series with
C37 and with varactor CR4 in series with C34. The dc voltage applied at the junction of CR4 and
Y2 controls the reactance of the parallel circuit, mainly through CR4. This dc voltage, controlled
4-35
Advertisement
