Advertisement
integer value. The terminal count from U29 is applied inverted by Q5 to this control input of U27.
The resultant divided signal at pin 9 of U29, U30 and U3l is applied to a
TTL
to ECL converter net-
work consisting of R30, R3l and CR7 to a flip-flop U2SA. This flip-flop reclocks the divided output
under control of the clock signal on U2SA pin 6 from the ECL output U27 pin S, and then applied to
one side of the phase comparator from its quadrature outputs on pins 2 and 3.
2. Phase Comparator and Pulse-to-Voltage Converter. The phase comparator reference is
derived from the 100 kHz signal from U 5 pin 12, reclocked against ·the 1 MHz reference in U26A.
The reference output at U26A pin 2 is applied to the other side of the phase comparator consisting
of U2SB,. U26B and U32. The ECL comparator provides phase comparator outputs at TP7 and.TPS.
The variable input from U28A pin is applied to a pulse-width detector consisting of CR9, CRIO, Q6
and U33B. As the pulse width changes as the frequency varies from 40.455 MHz to 70.454999 MHz
the voltage at the emitter of Q6 varies continuously and linearly over a range of approximately 1 volt.
The DC offset of this voltage is determined by the D/ A ref from U23. U33A and Q8 from one-half
of a current source to CR 12 and CR14 and Q7 and Q9 from the bottom half of this current drive
through CR13 and CR15. Phase compared outputs at TP7 and TP8 are fed into the diode network
formed by CR12, CR13, CR14 and CR15 and an output from this pulse-te-current converter is fed
to R60.
3. VCO and Analog Control Circuitry. The current output of the phase comparator is
combined with the voltage ramp from the D/A through C80. This combined signal is then applied to
an integrating amplifier U35. In normal operation, the output ofU35 is sent to a signal linearizing/
inverter circuit U37 A and to the out-of-Iock window detector comprising U34C and U34D. This is
described in more detail in the speed-up and 'out-of-Iock circuit operation. The output of U37 A at
TPlO is a DC voltage that can vary from a high voltage up to 18 volts and a low voltage equal to 1 volt,
it
will
be high voltage when the selected frequency is at 30 MHz and low when the system requires 0.5
MHz. This DC voltage is then passed through U37B which along with its associated resistors and.
capacitors forms a low-pass fIlter. This output is then buffered from the VCO by 120K resistor R88
between TPll and TP12. A further lead-lag network is then in the VCO control line between TP12
and ground formed by R92, R93, R94 and C9S. This voltage is then applied to the VCO control
varactors CR3 and CR4 through R85 and L4. A voltage applied to CR3 and CR4 will vary the
capacitance across the main VCO coil L5 and thus vary the frequency generated. Ql is the main La
active device and an output from its drain is capacitively coupled to a buffer amplifier of the cascade
type formed by Q12 and Q13. The output of this feeds the 2-modulus divider controller U27. A
further output from the oscillator coil is tapped off and provides the main La output through Q2
and Q3 with step down transformer Tl.
4. Speed-Up and Out-of-Lock Operation. When a large step of frequency is introduced
on the front panel or from remote the window detector U34C and U34D comparators, compares the
inputs on pins 9 and 10 from the VCO control circuitry with fixed high and low references on pins
11 and 8. If the voltage goes higher or lower (frequency step up or down) than these references
a pulse will appear at the comparator outputs on pins 13 and 14. This pulse is applied through an
RC network to a voltage converter consisting of U34B and CR19 and CR20. This voltage offset
pulse is then used to drive three switches U36B, U36C and U36D. These switches by- pass the
lowpass fIlter U37B and increase the integrating bandwidth of U35 and one switch, provides a feed
forward from TPIO to the positive input of U40. U40 provides an integrated drive to push-pull
drivers Q 10 and
Q
11, the action of these drivers is to high-speed charge or discharge C98 through
R91, C97 and R94. When the control voltage is at approximately the correct voltage for the fre-
quency selected this circuit becomes operative. U34A provides the Out-of-Lock signal for feeding
to the A9 Receiver control board and then to A6A2 for processing. If a pulse or a constant low level
is applied to pin 6 of U34A then its output will go low indicating OOL.
4-31
Advertisement
