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amplifier. These two signals are connected to transistor gate Ul9C which selects between the two sig-
nals on direction from Receiver control. In all modes except BITE the signal from the monitor output
amplifier is selected and routed to the AF metering circuit. This circuit is described unde.r AGC circuits.
4.3.4.3
AGe Control Circuits
Figure 4-7 illustrates a functional block diagram of the AGC circuitry contained on circuit
card assembly A4. ,The circuits consist of an AGC detector, AGC decay,. peak
signaLdetec~or,
decay
time constants, an integrator, fIlter, a
gain
control distribution amplifier, a digital to analog converter
and various electronic switches controlled from receiver control circuits. The'description also includes
the AF/RF meter comparator circuit.
The AGC circuitry is designed to provide three modes or techniques for controJling the gain
of the Receiver; Manual, Automatic and Automatic with a selectable threshold. In the automatic
mode the level of the IF amplifier U8 is controlled automatically with three selectable decay times;
SHORT, MEDIUM and LONG. In the manual mode the IF GAIN control is used to control the level
of the AGC signal applied to the IF amplifier U8. The IF GAIN control is used to select the threshold
in the automatic with selectable threshold mode. The same decay times as in automatic are selectable
in this mode.
An IF signal taken from IF emitter follower Q6 is coupled through capacitor C31 to U 1 OA
for detection. The three transistor array Ul a acts as a detector to the IF signal with UIOC connected
as an emitter for buffering the DC signal to two circuits; AGe decay and peak signal amplifier. Peak
signal amplifier U7C couples the signal, across a decay time select circuit, to integrator amplifier UI4A.
The signal routed to the hang circuit which consists of amplifier U7 A and U7B is time controlled
through capacitor C42, resistors R45 and Rl46 and transistors Q2 and QIO. When short time decay
is selected, Receiver control turns on transistor Q2 and transistor gate UI2A. Capacitor C42 is shorted
to ground through transistor Q2 which turns on transistor Ul aD and a short delay,is asserted using
combination resistors R52 and R55. When medium time decay is selected transistor QI0 and transistor
gate UllAis asserted. Capacitor C42 discharges through the parallel resistance of R45 and Rl46 pro-
viding a short hang time, after which UIO is turned on and a medium delay is asserted through R52 and
R53. When long time decay is selected capacitor C42 discharges through R45 providing a long hang
time, after which UIO is turned on, decay time is through R52.
The AGe applied to integrator amplifier Ul4A is mixed with signals from diversity AGC
through amplifier Ul4B and gain control or threshold from amplifier Ul4C when AGC mode dictates.
In the manual mode both transistor gates UIIC and Ul2B are enabled through receiver control and
the gain control voltage is asserted directly to the input of U14A. In the manual with automatic
threshold mode Ul2B is turned off and the voltage from the IF GAIN control asserts itself through
diode CR20 only when that level is higher than the AGe signal at the input of U14A. The digital
to analog converter is coupled through UIID and is used to insert threshold level from a remote
location through receiver control. Diversity AGC applied through transistor gate UIIC to the input
of Ul4C and to amplifier Ul4B influences the AGC signal only when its level is higher. When AGC
dump is enabled (during certain BITE modes and local/remote operations that require dumping of
AGC) receiver control enables flip-flop U9 A which turns on transistor Ul OE. This rapidly discharges
capacitor C52 thereby preventing U14A from acting as integrator.
The integrator amplifier is coupled to AGC filtering; consisting of capacitor C59, resistors
R76, R77, RBI and R83, diode CR21 and amplifier UI7A. If AGC dump is asserted (in certain
BITE modes) transistor gate U12D is turned on providing a much faster charge patch for C59 through
resistor R7B. The output of the filter amplifier U17A is coupled to amplifier U17B. This amplifier
provides the AGC signal to IF amplifier UB. At the same time Ul7B provides one input to A3 AGC
drive amplifier Ul7D through diode CR26. If ISB is installed and enabled a second AGC signal
4-21
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