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,
-\
\
4 x 4 Multiport Register U22, and at the Al through A8 inputs to UIS. If no new data is loaded into
U8 through U12 from the serial input data stream, then the two cycles of accumulation will continue;
first accumulating the contents of U8 through U 12 on one half cycle with the data at Al through A8
in UIS, and on the second half cycle adding the results from the first accumulation back into the B
inputs of UIS. Temporary storage for the results of each accumulation is provided by U18, U20 and
U21.
If the result of adding numbers in VIS is a terminal count, the adder will produce a Carry-·
Out pulse at UIS pin 6 and reset to zero and start counting again. In a real situation this process is on
going and the addeiis continually providing Carry-Out pulses. (See Figure 4-12, line B.) This Carry-
Out pulse is fed to
V6
to be rec1ocked. The rec10cked output at U6 pin 7 is routed through UIC to a
further adder U17. The carry out is also clocked by U19A so that if it occurs on one edge of the ac-
cumulating half cycle controlled from U4B, it will appear at the Q output ofU19A and after reclock-
ing in U6 through the fifth latch it is applied to the carry input of the 4-bit full adder V17. (See
Figure 4-12, line C.) The adder U17 continually updates,by addition, based on the carry out informa-
tion from UlS, the 100 kHz frequency information, provided by the input storage register V13. The
addition in· this adder is continuous so that the outputs at U17 pins 10 through 13 are constantly
changing to provide the averaging action previously discussed.
For DAC control, a 4 x 4 multiport register U22 provides storage for the results of the
constant accumulations and provides the information to the digital-te-analog converter V23. U19B
divides the accumulator control signalbytwc{sothat all four registers in U22 can be loaded. The
read cycles to these registers are controlled by the R0A, R0B, RIA andR1B inputs of U22. The
R0A and R0B inputs are fixed and the RIA and RIB inputs are controlled by the output of Ul9B
. so that during two accumulations Rl is loaded, each register R0 andRl consisting of two 4-bit data
storage areas. The data stored is that which appears at the data inputs orU22, D0tlir6ugh D3. This
stored information is transferred
to
the register Aoutp·uts. and register B
outpu·~wheh
\VEnable is
high and either W0 is high transferring R0A and R0B contents or Wl is high transferring the contents
ofR1Aand RIB.
The digital-te-analog converter provides an output based on the changing data at its inputs
as a voltage ramp whose amplitude and DC offset
is
modified by the adjustment of R5. The D/A also
provides a reference source for the pulse to voltage converter U33.
NOTE
The pulses demonstrated in Figure 4-12 can be reproduced in circuit if
the RF front panel frequency is set to 1.046000 MHz and the test points
TPI and TP2 temporarily shorted. This ensures that the accumulations
start from a zero condition. B will then be at TP3, C at TP4 and E at
U23, pin 2 (the D/A output).
4.3.6.3
Oscillator Control
Figure 4-11 presents a simplified bloek diagram of the oscillator control circuits. To more
fully understand the operation, the following description is divided into four principal areas; 1) Main
Division, 2) Phase Comparator and Pulse-to-Voltage Converter, 3) VCO and Analog Control Circuitry.
and 4) Speed-Up and Out-of -Lock Operation:
1. Main Division. The BCD data outputs for 100 kHz, 1 MHz and lO MHz provided by
Ul7 and U14 are applied to a 2-modulus, 3-decade divider consisting ofU27, U29, U30 and U31.
This form of division ensures that by using a 2-modulus high speed control device U27 that can divide
by 10 or 11 under control ofits M 1 and M2 input control can divide a high frequency input by an
4-29
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