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or minus 8 kHz through receiver control. The oscillator operates in a phase locked loop which con-
sists of a voltage controlled oscillator (VCO), a buffer amplifier, a programmed divider, a phase
comparator and a digital to analog converter. A divide by 2000 circuit is included to provide a 500
Hz reference signal for the phase comparator. The VCO operates at a center frequency of 22.75
MHz which is 50 times the BFO center frequency of 455 kHz. The oscillator output is routed through
a buffer amplifier, TTL shaper, divide by 50 circuit and fllter to provide the 455kHz BFO to the
A4 circuit card.
An
out of lock (OOL) circuit is also included to detect. any out of lock condition of
the phase lock loop.
.
1. Phase. Lock Loop.
Th~
phase lock loop for the BFO oscillator functions in ,the same
way as the circuit described for the second local oscillator except the divide by N is made variable
through BFO input data to the divide by N circuit.
2. Voltage Controlled Oscillator. The VCO consists of field effect transistor Q 18 opto
isolator U21, coils L4 and L5, resistors R66 and R67, capacitors C52 through C56 and C59 and
varactors CR6 and CR7. The capacitive reactance of the two varactors in conjunctions with L4
determines the frequency at which the circuit will oscillate. Since varactors change capacitance
in relation to the level of the dc voltage applied, the frequency of the oscillator is controlled from
the output of the digital to analog converter that is applied to varactors CR6 and CR7 through
coil L3. Opto isolator U2l , connected to the source of Q 18 through resistor R67, provides for on-
off control of the oscillator by isolated control of the oscillator source bias. When BFO is enabled
in the CW and sideband modes, U21 is enabled through pin 2 which in turn completes the bias path
for Q18 through R67.; The output of the oscillator is coupled through capacitor C57 to the gate of
field effect transistor Q19 which acts as a buffer amplifier between the oscillator and two output
circuits. One output of the buffer amplifier provides the oscillator reference frequency through
capacitor C72 to the programmed dividers. This circuit is described in Paragraph 3. The second out-
put is coupled through capacitor C60 to a shaper circuit, Q20, R72, R73, R74 and C61. This circuit
shapes the waveform into a square-wave for the TTL logic' of the divide by circuit U20. The dual
decade counter U20 is externally strapped to provide a division of 50 on its QD output, pin 9. The
variable 22.35 to 23.15 MHz oscillator signal is reduced in frequency by the division of 50 which
provides the 447 to 463 kHz BFO. This output
is
flltered through the filter network consisting of
C63, C64, C65, L6, R75, R76 and R77. This fllter shapes the digital waveform from U20 into an
approximate sine wave signal before being routed to circuit card A4 through connector 14.
3. Programmed Dividers. The programmed dividers determine the divide by N number
by which the oscillator frequency
will
be divided for a variable reference to the phase comparator.
The program dividers consist of presettable BCD decade counters U14 through U18, divide by 10
, or 11 2-modulus controller U19, NOR gates U12A through U12D and AND gates U13A through
U13C. The program divider has two reference inputs; the oscillator frequency coupled through
C72 to the V reference and clock inputs ofU19 at pins 15 and 16 and the BFO data control inputs
to Ul5 through U18. It is the BFO data inputs in conjunction with U19 that sets the divide by N
number for dividing the VCO frequency. To divide the 22.75 MHz to 500 Hz, for the second clock
input to the phase comparator, would require a division of 45500. The five decade counters are
externally strapped to count down from a maximum count of 100000 (99999 + 1). The actual data
then that would be set on the BFO inputs would be 100000 - 45500
=
54500; however due to
gating restrictions between the decade counters the actual number set at the BCD inputs is 54509 at
center frequency (455 kHz). The BFO is adjustable plus or minus 8 kHz so that the swing in the
BCD inputs must be from 53709 (54509 - 800) to 55309 (54509 + 800) with 54509 as center. At
center frequency counter UI8 receives the 10 Hz BCD digits on its parallel inputs PO through P3
with PO and P3 (2 0 + 24 = 9) high. Counter Ul 7 receives the 100 Hz digits with
all
input low (0),
U16 receives the I kHz digits with PO and P2 (2 0 + 22
=
5) high, and U15 receives the 10 kHz digits
with only P2 (22
=
4) high. Counter U14 is strapped PO and P2 (20 + 22
=
5) to the +5 volts (high)
4-39
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