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BCD to 1 of 10 decoder U 1. This decoder has only one output high at a time as directed by the BCD
input. This allows selection of fIlter slots FL2 through FL 7 in accordance with the three digit BCD on
the data line as clocked by strobe 12 on the clock input of U2. The Q4 output of U2 is routed directly
to the diode switch of FLI which is used to select that fIlter slot at the appropriate program time.
Data through data latch U4 is used to control the RF switch that selects between BFO and the IF
signal for input to the limiting amplifier and FM detector and D flip-flop U9A. This flip-flop controls
the AGC dump line. Data latch U4 is also timed by strobe 12. Data through data latches U'l3 and
UlS control switches in the AGe circuits for various AGe modes. These latches
ar~
timed through
strobe 13. The output of data latch
U23,
timed by strobe 15, controls the detector select switch
Ul9
A,
an audio fIlter level c.ontrol switch UI9B and an AF meter audio select switch U 19C. All
eight data lines are connected to the digital-ta-analog converter for digital control of its analog output. '
This unit is timed through strobe 14 and is used to provide analog-to-digital conversion of the DIV
AGC line and audio line by peak detector U22A using a successive approximation technique. The
digital information gathered by the microprocessor is used for front panel metering. Five data lines
are'routed to crosspoint switch U2S which is timed by strobe SIS. The audio function of the cross-
point switch along with other A4 functions controlled through A9 are described under the A4 circuit
card in Paragraph 4.3.4.
e. Circuit Card AS Functions. Two data latches on the AS circuit card are used to
control AGC circuit functions on this circuit card. The two latches U7 and U8 have AS reference
designators and are shown on the AS schematic diagram in Figure
7-5.
The 8-line data bus from
translators (described in Paragraph d) on ·the A4 circuit card are routed to the data latches with strobe
10
timingboth latches through transistor Q6, also located on AS. The data output from the latches
is used to control the AGC circuits described under the AS circuit card in Paragraph 4.3.5.
' .
.
f.
Out of Lock (OOL) Functions. Three out of lock circuits, that monitor the condi-
. tion ofthephaselock loops of the three oscillators, drive OOL indicators on the A9 circuit card and
supply their output data to the microprocessor. This data is routed through circuits on the
A9
card
that drive a fault indicator on the front panel and also a fault indicating circuit that provides a TTL
level related to the FAULT condition to connector 13 on the rear panel via A4 circuit card. The
three OOL circuit outputs from the three oscillator phase lock loops are connected to the S inputs
of dual D flip-flops U4S and US4. These flip-flops are clocked from address multiplexer U29. With
the data and reset inputs tied to ground (low) and the S inputs low (phase lock loop in lock) the Q
outputs of the flip-flops will be low. If an S input goes high (out of lock) its Q output will go high
causing a low through its respective inverter U44A, U44B or US3A. This in tum will enable the ap-
plicable LED indicator DS I, DS2 or DS3. These LED indicators are located on the A9 circuit card
for accurate determination of the OOL circuit. The Q outputs of the flip-flops are also connected to
the inputs of buffer U43 which is also timed by multiplexer U29. The buffer, in program sequence,
outputs the status of the OOL circuits on the data bus which is then routed to the microprocessor. The
processed FAULT data is routed through binary counterU51 and decoders U63 and U64. The Q5
(F AULT) output of decoder U63 is routed through inverter US2B to the rear panel while the Q5
(FAULT) output of U64 drives the front panel fault indicator through inverter U52A.
g. AF/RF Meter Comparator Functions. The main RF, ISB RF; and AF comparator
circuits along with an ISB fitted circuit from the A4 circuit card are connected to four inputs of non-
inverting buffer U42A. The inputs are strapped to +5 volts through 22K ohm resistors in resistor
array U41. When the optional AS circuit card is installed, input II is strapped low through·a ground-
ing circuit on that card. The three comparator input (12, I3 and 14) levels depend on the comparator
outputs. Buffer U42 is timed from multiplexer U29 and in program sequence transfers the compara-
tor data as used by A6A2 in a successive approximation technique to generate a bar graph for front
panel display to data lines FPO, FP 1 and FP2 and the ISB fitted status to data line FP4.
4-47
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