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U22, and is routed directly to U3, US and U18. The Hex D flip-flops U3 and US with UlA and
Ul B provide a 10-level, ring counter. This counter is used to provide timed pulses to clock the
accumulator from first accumulation to second accumulation and sequentially clock out the data
in the latches U8 through U12 to the full adder UlS. Flip-flop U3 provides a pulse 1 clock pulse
wide but delayed 5 pulses from D0 the input, to Ql the output. The output at U3Q4 is connected
to the input D0 of US. US also provides 1 clock pulse wide pulses but each output Q0 through Q4
is used to drive the incoming data latches. U4A and U4B convert the narrow pulses from U3 Q0
and US Q0 into a 50% duty cyclesquare wave with a period of 10 clock pulses (each half cycle
5 clock pulses long). The 180
0
out-of-phase outputs at U4A pin 1 'and U4B- pin 4 provide control
to U2, U22 and U19 to ensure that these devices are enabled during the correct half cycle. The 100
kHz reference for the reference side of the phase comparator is taken from US output Q4 .. US out-
put Q0 is provided to U4C via U7C to reclock the CARRY IN to Ul5 and also to U6 to provide
the
cloc~
for.
alignment of signals out of the HEX D flip-flop U6.
In serial-to-parallel conversion, the incoming serial data stream from the A9 Receiver
control assembly consists of DATA, CLOCK and STROBE signals. The strobe is routed to U6 in-
put Dl where its output is reclocked. This output at U6 QI is fed back to D2 and its output Q2
provides a strobe input to'U13 and UI4 one clock pulse delayed. The incoming CLOCK is fed to
Ul4 through U8 in parallel. The serial DATA is fed first into UI4 which from its output on UI4
pin 10 to UI2 and Ul3 shift registers. The output from Ul2 at pin 10 is fed to UIO and UII, and
so on to U9 and U8 to complete the data load and forming the serial-to-parallel conversion of syn-
thesizer data into the data registers. The data registers U8 through U14 hold the data for the
synthesizer frequency, the U8 register holding the 4-bit BCD data for the 1 Hz digit and each
register the next decade so the U9 register holds the 10Hz data and so on to the U 14 register which
holds the 1 MHz and 10 MHz data.
If the front panel RF frequency is set to 10.426800 MHz.then the actual ioaded data is
39.255 MHz above this frequency which is 49.680800. The first IF frequency is 40.455 MHz so
we can see that a further offset of 1.2 MHz less than the main LO frequency of 50.881800 is intro-
duced by the microcomputer into the serial data stream sent to A7. This is accounted for in the
actual mathematical process in the first and second accumulator circuitry, which replaces this off-
set before generating the final VCO control voltage to the local oscillator
With accumulator operation, the data loaded into the registers U8 through Ul2 is fed in
4 parallel boards under control of the ring counter US during the first half cycle of the tuning as
discussed in the tuning section to the Full NBCD Adder UI5. As the accumulation proceeds, the
accumulating sum is passed from the sum outputs of UIS to the 4-bit wide latch U18. The Carry
. Out signal from UlS is also stored in Ul8 and is clocked out to U7 A and then under control of U7C
from the tuning circuits through U4C back into the Carry-In port of U15 deriving the first accumu-
lation the outputs from Ul8 will be propagated through into the 4 stage shift registers contained in
U20 and U2l. U20 and U2l are 18 stage registers divided each into 2 four stage registers and 2 five
stage registers. The four outputs from UI8 are fed into the 4-stage registers in each half of each U20
and U2l and then the output of these 4-stage registers is fed back to the 5-stage register in each half
of U20 and U21 At the end of the first accumulation
~he
data at the output of the 4-stage register
appears at the input to the tri-state 4-bit buffer U2A.
As
the second accumulation begins U2A is enabled, under control of U4A, and the data
at its inputs is transferred to the B inputs of UIS the NBCD Adder. During the five clock periods of
the second accumulation the data in U20 and U21 is shifted back to the
B
inputs of UlS. During
this period, the data in U8 through U 12 is held as the tri-state output enable of these registers is not
enabled ensuring the results of the first accumulation is added again in the second accumulation. At
the end of the second accumulation the results of the first accumulation will be propagated through
the 5-stage register in each half of U20 and U21 and
will
appear at the inputs Dfi) through D3 of the
4-27
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