Advertisement
and PI and P3 to
~ound
(low). This supplies the 100 kHz digit which is always 5. Counter UIS
receives only the 2 0 , 21 and 22 BCD digits smce the 10kHz swing is never greater than 7. The
counter is a two modulus divide by 10 or 11 controller and will divide by 10 or 11 for different
periods in the clock signal. The TC output of UI8 coupled to the M l-M2 inputs of U19 determine
the periods at which it will divide with either 10 or 11. NOR gate U12C ensures that the count
enable input of UI8 goes low when TC goes high. This assures that the TC output will be retained
long enough for action on the MI-M2 inputs ofUl9. The QTTL output (pin 11) is used to clock
the decade
coun~ers
U14 through UI8 and as a reclocking source for NOR gate U12A. . Four control
inputs, paralleI-enable (PE), count enable parallel (CEP), count enable trickle (eET) and reset (R)
, .
seleqt the counters mode. of operation. The Rand CET of all counters
is
held high through the +5
volts connected to all counter CET and
R
inputs. The CEP input of counter Ul7 (100 Hz) is also '.
held high from the same +5 volts since this counter does not receive a carry out from previous counters.
The CEP of counter Ul6 is high only when the TC output of U17
is
high, the CEP of UlS is high only
when the TC output of both CI6 and CI7 through AND gate UI3A are high and the CEP input of
U14 is high only when the TC output of both UlS and Ul6 through AND gate U13B are high. This
AND gating of the TC outputs help prevent extra pulses from occurring that are caused from delays
- in the counters. The PE of all counters are alternately low and high as the TC output to inyerter
Ul2B is alternately high and low. With the Rand CET of all counters held high (counter resets when
R
is
low) the count mode is enabled when CEP and PE goes high. When PE goes low the counters will
synchronously load the data from the BFO inputs into the counters with the count occurring each
500 Hz. The counters output on TC only when PE is held high; however when CEP is held low the
TC output will be retained until the next clock pulse. The TC output of the programmed dividers is
connected to one input of a two input NOR gate UI2A. The clock signal is connected to the second
input so that any unwanted pulses, created by delay in the counters and not in sequence with the
clock pulse will be rejected. The output of Ul2A
is
routed through inverter U 12D to one clock input
of the.phase comparator as the .oscillator reference frequency.
,>
4; Reference Frequency. The 1 MHz reference frequency supplied from internal/external
reference circuits
is
divided by 2000 to provide a 500 Hz reference frequency to the phase compara-
tor. This division of 2000 is accomplished with two dual decade counters U8 and U9. Counter U8
provides a division by 100 while counter U9 provides division by 20. Each counter has two divide by
2 circuits and two divide by 5 circuits and are externally strapped to provide the divisions by 100 and
20. The division by 100
is
accomplished by using all four dividers in the order shown
(~
2
=
500 kHz.
~
5
=
100 kHz,
~
5
=
20 kHz and +2
=
10kHz). The divide by 20
is
accomplished in the same manner
except its input is the 10kHz output of the
~l
00 and the second
~
5 is bypassed
(~2
=
5 kHz,
~5
=
I kHz, and
~
2
=
500 Hz). The resultant 500
Hz
output is coupled to the clock input of D flip-
flop UIOA. .This flip-flop
is
contained in a dual flip-flop package which together with NOR gate UIIA
make up the phase comparator.
5. Phase Comparator and Digital to Analog Converter. As described previously, the 500 Hz
reference frequency
is
connected to flip-flop UI0A. The second flip-flop Ul OB rece1ves its clock sig-
. nal from the programmed dividers. The D inputs of both flip-flops are tied to the +5 volts (logic 1)
while both Q outputs are connected through 2 input AND gate UIIA and resistor R83 to the reset of
both flip-flops. Both flip-flops will reset each time that both Q's go high, causing a logic
a
at the resets
of both flip-flops. The clock input signal to U 1 OA (reference) consists of positive going pulses while the
signal from the programmed divider (oscillator reference) also contains positive going pulses and is
connected to the clock input of· UI OB. Each flip-flop triggers
Q
on (high) the positive going pulse of
its respective clock signal and at the same time triggers
Q
to zero (low). Previously as described, when
both Q outputs are high the output from AND gate UIlA is low clearing both flip-flops through R83.
This resets the
Q
outputs to low and the
Q
outputs to high. Refer to Figure 4-14. The two
Q
outputs
are connected to the digital to analog converter which consists of transistors Q 15, Q 16 and Q 1 7 and
their associated components. This circuit operates in the same manner as the digital to analog converter
4-40
Advertisement
