Operation Complete Definition; Table 3.3 Default Settings For Output Off Registers - ILX Lightwave LDC-3926339 User Manual

R E M O T E O P E R A T I O N S
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C H A P T E R
Status Reporting

Table 3.3 Default Settings for Output Off Registers

LASER1 Output Off Register
0- disabled
1- disabled
2- n/a
3- enabled
4- n/a
5- n/a
6- n/a
7- n/a

Operation Complete Definition

Bit 0 of the Standard Event Status register contains the status of the Operation
Complete flag. Enabling this bit via the *ESE command allows you to update Bit 5
of the status byte. Then, if the SRE mask has bit 5 set, and you issue an *OPC
command, the SRQ signal is generated upon completion of the currently
processed commands. This is used to initiate service request routines that
depend on the completion of all previous commands.
The LDC-3926339 defines Operation Completeness as the state when all
sequential and overlapped commands are completed. Most commands are
sequential; only a few are overlapped. See Sequential/Overlapped Commands on
page 29 and refer to your module instruction manual for a list of overlapped
commands.
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LDC-3926339
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8- n/a
9- disabled
10- n/a
11- n/a
12- n/a
13- n/a
14- n/a
15- n/a