Allen-Bradley 1779-KFMR User Manual page 76

Frame Check Sequence Field
All frames include a 16-bit frame check sequence (FCS) field just prior to
the closing flag. The FCS is also referred to as the cyclic redundancy
code (CRC). The FCS provides a high level of data security. The FCS
can detect:
All Single-Bit and Double-Bit Errors
All Errors of Odd Numbers of Bits
All Burst Errors of 16 Bits or Less
99.997% of 17-Bit Error Bursts
99.998% of 18-Bit and Larger Error Bursts
The FCS algorithm checks the integrity of the address, control, and data
fields. However, the zeros inserted into the data field to maintain
transparency ("Zero-Bit Insertion") are excluded from the algorithm. The
FCS is the remainder of a division process in which the fields are treated
as a single value. The value of these fields is divided by the polynomial:
The polynomial is that used in the International Telegraph and Telephone
Consultative Committee (CCITT) Recommendation V.41,
Code-Independent Error Control System.
Abort
If a node wants to abort a frame it is transmitting, it must end the frame in
an unusual manner such that the other node will ignore the frame.
A node aborts a frame by transmitting at least seven contiguous ones
(with no zeros inserted). A node receiving a frame interprets seven
contiguous one bits as an abort.
Zero Bit Insertion
Because the flag sequence delineates the beginning and ending of each
frame, the flag sequence must not appear in any of the other fields of the
frame. Also, seven or more ones must not appear unless an abort is
intended. Although these bit patterns may also appear in message packets
sent down from the preceding layer, false flag and abort sequences are
avoided by zero-bit insertion as follows:
Chapter 6
HDLC Data Link Layer
16 12 5
x + x + x + 1
6 7