I
'"
32
Direct Virtual Memory Access
Direct Virtual Memory Access
315
32.1. A Generic DVMA Cycle
315
32.2. Optimizations to the DVM A Cycle
316
Back-to-Back DVMA
316
Ethernet
Hold
316
V1-IEbus Lock
316
32.3. Refresh as a Special Case
316
32.4. The DVMA Strobe PAL (U241 0)
317
Input and Output Signals
319