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224
2060 CPU Board Engineering
Manual
CONFIDE~TIAL!
4.
e_reset- : resets the Ethernet controller.
U1405 read buffer's outputs are held static to the Ethernet controller until the
buffer is either cleared or new data is clocked into it by the rising edge of
wr_ether-. U1405 is cleared (all
Q
outputs
are
set to zero) by the assertion of the
init- signal.
U1407 Ethernet Control Read
Buffer
25.7..
System Enable
Register
U1406 System Enable Write
Register
U1407 ALS 373 acts as a read-back register to the write outputs of the U1405
write register. The four control signals from U1405
are
connected to U1407:
1.
e_inten-: interrupt enable to the controller
2.
e_ce : chip enable to the controller
3.
e_loopb- : sets the Ethernet chip into loopback node
4.
e_reset- : resets the Ethernet controller.
Also connected to the U1407 read register are the signals:
1.
e_int : interrupt signal from the Ethernet controller
2.
e_err : error signal from the Ethernet chip
Since the interrupt and error signals occur asynchronously to the processor, they
must be s)TIchronized through UI407. Data at the input(s) of U1407 are latched
to the TrL data bus (t_d[7:0]) by the assertion of the rd_ether- strobe from
U1401. When the rd_ether- strobe is high (deasserted) the U1407 read buffer is
set to a high impedance state.
The U1406 and U1408 system enable register operates the same as the Ethernet
control register. Write data is clocked into U1406, and U1408 acts as a read-
back register.
Write data is clocked from the 1TL data bus into the U1406 register on the rising
edge of the wr_sysen- signal, which goes inactive at the end of the write cycle.
Write signals output from U1406 are:
1.
fpaen : enable signal to the FPA
2.
encopy : enables copy mode to the video buffer
3.
envideo : enables output from the video section
4.
en_cache: enables cache memory
5.
en_sdvma: enables supervisor DVMA
6.
en_fpp : enables the floating point processor
7.
en_boot- : enables boot
state.
{Rev 1 of 10 May 1987} CONFIDEl''TlAL!
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