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Sun Microsystems SME5224AUPA-400 Datasheet
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Sun Microsystems SME5224AUPA-400 Datasheet

Sun Microsystems SME5224AUPA-400 Datasheet

Ultrasparc-ii cpu module 400 mhz cpu, 4.0 mb e-cache
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DATASHEET
M
D
ODULE
ESCRIPTION
The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400) delivers high performance
computing in a compact design. Based on the UltraSPARC™-II CPU, this module is designed using a small
form factor board with an integrated external cache. It connects to the high bandwidth Ultra™ Port Architec-
ture UPA bus via a high speed sturdy connector. The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, can
plug into any UPA connector, saving system design costs and reducing the production time for new systems.
Heatsinks are attached to components on the module board. The module board is encased in a plastic shroud.
The purpose of this shroud is to protect the components and channel airflow. Module design is geared
towards ease of upgrade and field support.
Module Features
Ease of System Design
Performance
Glueless MP Support
Simplify System Qualifications by
Complying with Industry and Government
Standards
UltraSPARC
Module Benefits
• Small form factor board with integrated external cache
and UPA interface
• JTAG boundary scan and performance instrumentation
• PCB provides a multi-power plane bypass, reducing
systemboard design requirements
• High performance UltraSPARC™ CPU at 400MHz
• Four megabytes of external cache using high speed
register-latch SRAMs
• Dedicated high bandwidth bus to processor
•
• Implements the high performance AUPA interface
• Supports up to 16 Mbyte of external cache in a
four-way MP system
• Backwards compatibility with systems implementing a
UPA interface
• Plastic shroud protects components and channels
airflow
• Multi-layer PCB controls EMI radiation
• Edge connectors and ejectors
• Small form factor board encased in a heat resistant
shroud
• On-board voltage regulator accepts 2.6 volts for the
Vdd_core; compatible with existing systems
SME5224AUPA-400
™
-II CPU Module
400 MHz CPU, 4.0 MB E-Cache
July 1999
1

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Summary of Contents for Sun Microsystems SME5224AUPA-400

  • Page 1 ODULE ESCRIPTION The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400) delivers high performance computing in a compact design. Based on the UltraSPARC™-II CPU, this module is designed using a small form factor board with an integrated external cache. It connects to the high bandwidth Ultra™ Port Architec- ture UPA bus via a high speed sturdy connector.
  • Page 2 • 1.6 Gbyte/sec (peak) with a 100MHz UPA • Delivering high performance access to large datasets across the network • Enabling UltraSPARC™ based systems to offer features such as: power management, automatic error correction, and lower maintenance cost Sun Microsystems, Inc July 1999...
  • Page 3 1.9V HSTL. The SRAM clock is a differential low-voltage HSTL input. 1. PECL (Positive Emitter Coupled Logic) clocks are converted on the module to the HSTL clocks, for the E-cache interface. July 1999 UltraSPARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache Sun Microsystems, Inc Advanced Version SME5224AUPA-400...

  • Page 4: Block Diagram

    400 MHz CPU, 4.0 MB E-Cache ODULE OMPONENT VERVIEW The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), (see Figure 1), consists of the following components: • UltraSPARC™-II CPU at 400 MHz • UltraSPARC-II Data Buffer (UDB-II) • 4.0 Megabyte E-cache, made up of eight (256K X 18) data SRAMs and one 128K X 36 Tag SRAM •...
  • Page 5 24 and page 25. UPA Interconnect The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), supports full master and slave functionality with a 128-bit data bus and a 16-bit error correction code (ECC).
  • Page 6 The JTAG TCK signal is distributed to UDB-II, SRAMs and the CPU. For additional information about the JTAG interface, see "JTAG Testability," on page 22, and "JTAG (IEEE 1149.1) Timing," on page 23. ™ -II CPU Module at 3.3V, and V DD_CORE Sun Microsystems, Inc at 2.6V. The V supplies the DD_CORE July 1999...
  • Page 7 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. July 1999 UltraSPARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache Name and Function Name and Function Sun Microsystems, Inc Advanced Version SME5224AUPA-400...
  • Page 8 POWER_OV Connected to GND via a 1180-ohm resistor. Sets overvoltage level for programmable supply. 1. The thermistor used on the module (SME5224AUPA-400) is manufactured by KOA. Operating at 47K the thermistor has KOA part number NT32BT473J. ™ -II CPU Module...
  • Page 9 The block diagram for the LVPECL clocks "Clock Signal Distribution," on page 10, illustrates a typical system clock distribution network. Each clock line is a parallel-terminated, dual trace LVPECL clock signal for the CPU, the UPA and the SRAM devices. July 1999 Sun Microsystems, Inc...
  • Page 10 FR4, PCB Dielectric. ™ -II CPU Module CPU_CLK Module Connector UDB-II UPA_CLK0 UDB-II UPA_CLK1 UPA_CLK Clock Buffer UPA_CLK2 UPA_CLKx Sun Microsystems, Inc Module Boundary SRAM SRAM SRAM SRAM SRAM Clock Buffer SRAM SRAM SRAM SRAM/TAG UltraSPARC-II UPA Device UPA Device...

  • Page 11: Recommended Operating Conditions

    , except when the CPU is being re-cycled, at which time the V ground. 3.14 3.30 2.47 2.60 – – -0.3 – – – – – – – – – Sun Microsystems, Inc Advanced Version SME5224AUPA-400 Units Units 3.46 2.73 – + 0.2 – . See the section...
  • Page 12 , are respectively 3.30V and 2.6V. The estimated maximum power consumption of the DD_CORE UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module (SME5224AUPA-400) is 70 watts at 400 MHz. The estimated maximum power consumption includes the CPU, the SRAMs, the clock logic and the 8 watts consumed by the DC-DC regulator.
  • Page 13 3.1 nH Trace 3 1.0 pF 1.0 pF 7 pF Measure point for XB1 XB1 BGA Package Loading Measure point for CPU Sun Microsystems, Inc Advanced Version SME5224AUPA-400 Trace 4 via 0.6 pF 7 pF UDB-II of Second Module Package Loading...
  • Page 14 Setup Signals and Hold Time Signals UPA_DATA [127:0] Setup time UPA_ADDR [35:0] UPA_ADDR_VALID, UPA_REQ_IN [2:0], UPA_SC_REQ_IN, UPA_DATA_STALL, UPA_ECC_VALID, UPA_RESET_L, UPA_XIR_L UPA_ECC [15:0] UPA_S_REPLY [3:0] ™ -II CPU Module Waveforms Sun Microsystems, Inc 400 MHz CPU 100 MHz UPA Unit – – – – July 1999...
  • Page 15 2.4V Rising Edge Output 0.8V 0.4V 2.4V 2.0V Falling Edge Output 0.8V 0.4V Waveforms 2 Sun Microsystems, Inc Advanced Version SME5224AUPA-400 400 MHz CPU 100 MHz UPA Unit – – – – 400 MHz CPU 100 MHz UPA Unit –...
  • Page 16 ™ -II CPU Module Front SRAM Heat Sinks 6.250 [158.75] 5.890 [149.61] 0.112 [2.86 ] 2.551 [64.79] Dimensions: inches [millimeters] Sun Microsystems, Inc Module Ejectors CPU/Voltage Regulator Heat Sink Thermistor Location (RT0201) 0.179 [4.55] 3.680 [93.47] 0.570 [14.48] Pin 1 0.174 [4.41]...
  • Page 17 NOTE: A minimum backside clearance is required for airflow cooling of the backside heatsink. July 1999 UltraSPARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache Figure 8. CPU Module Side View Sun Microsystems, Inc Advanced Version SME5224AUPA-400 Module Shroud Bidirectional Airflow...
  • Page 18 In addition, the lower the junction temperature, the higher the system reliability. The CPU temperature must be verified under a range of system compute loads and system environmental conditions, using one of the temperature measuring methods described herein. ™ -II CPU Module Sun Microsystems, Inc July 1999...
  • Page 19 Accuracy of this value requires that good thermal contact is made between the package and the heatsink. This value is dependent on the heatsink design, the airflow direction, and the airflow velocity. The ducted airflow. Sun Microsystems, Inc Advanced Version SME5224AUPA-400...
  • Page 20 Airflow Bottomside 100 LFM @ 30 C up to 2,000 feet, altitude, maximum 150 LFM @ 40 C up to 10,000 feet, altitude, maximum ™ -II CPU Module 0.91 0.84 0.78 Sun Microsystems, Inc 1000 0.72 0.67 0.64 July 1999...
  • Page 21 If the heatsink temperature (Ts) is known then the following ther- mal equation can be used to estimate the junction temperature: Tj = Ts + [Pd ( jc + cs)] July 1999 Sun Microsystems, Inc...
  • Page 22 JTAG T ESTABILITY The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), implements the IEEE 1149.1 standard to aid in board level testing. Boundary Scan Description Language (BSDL) files are available for all the active devices on the module, except the clock buffer.
  • Page 23 In-Phase Out-of-Phase Figure 11. Voltage Waveforms - Propagation Delay Times July 1999 UltraSPARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache Clock 2.0V 1.5V 1.5V Clock 2.0V 2.0V Output 0.8V Output 0.8V Sun Microsystems, Inc Advanced Version SME5224AUPA-400...
  • Page 24 UPA_DATA[34] UPA_DATA[32] UPA_DATA[22] UPA_DATA[20] UPA_DATA[18] UPA_DATA[16] UPA_DATA[6] UPA_DATA[4] UPA_DATA[2] (Pin 319) UPA_DATA[0] GND (Pin 320) GND (Pin 326) Sun Microsystems, Inc GND (Pin 5) GND (Pin 11) VDD_CORE VDD_CORE VDD_CORE VDD_CORE UPA_PORT_ID[1] VDD_CORE VDD_CORE GND (Pin 137) GND (Pin 143)
  • Page 25 UPA_DATA[40] UPA_DATA[30] UPA_DATA[28] UPA_DATA[26] UPA_DATA[24] UPA_DATA[14] UPA_DATA[12] UPA_DATA[10] UPA_DATA[8] (Pin 321) (Pin 320) GND UPA_CLK1_POS (Pin 327) (Pin 326) GND Sun Microsystems, Inc Advanced Version SME5224AUPA-400 UPA_ADDR[9] (Pin 6) UPA_ADDR[11] (Pin 12) UPA_ADDR[13] UPA_ADDR[15] UPA_ADDR[25] UPA_ADDR[27] UPA_ADDR[29] UPA_ADDR[31] UPA_ADDR_VALID UPA_REQ_IN[0]...
  • Page 26 SRAM heatsinks because this action can cause unseen damage to the solder connections. Always handle modules and other electronic devices in an ESD-controlled environment. ™ -II CPU Module Conditions Min. – – – Sun Microsystems, Inc Value Typ. Unit – – C/min. – inches –...
  • Page 27 Re-organization of the datasheet and update of specifications. New section concerning the System Timing and Thermal Specifications. Revised specifications for DC characteristics and module power consumption. Illustrations reflect a new heat sink design. Thermal section reflects the latest heatsink design. Sun Microsystems, Inc Advanced Version SME5224AUPA-400...
  • Page 28 Sun Microsystems, Inc. Sun, Sun Microsystems, the Sun Logo, Ultra, and VIS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries.
  • Page 29 ODULE ESCRIPTION The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400) delivers high performance computing in a compact design. Based on the UltraSPARC™-II CPU, this module is designed using a small form factor board with an integrated external cache. It connects to the high bandwidth Ultra™ Port Architec- ture UPA bus via a high speed sturdy connector.
  • Page 30 • 1.6 Gbyte/sec (peak) with a 100MHz UPA • Delivering high performance access to large datasets across the network • Enabling UltraSPARC™ based systems to offer features such as: power management, automatic error correction, and lower maintenance cost Sun Microsystems, Inc July 1999...
  • Page 31 1.9V HSTL. The SRAM clock is a differential low-voltage HSTL input. 1. PECL (Positive Emitter Coupled Logic) clocks are converted on the module to the HSTL clocks, for the E-cache interface. July 1999 UltraSPARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache Sun Microsystems, Inc Advanced Version SME5224AUPA-400...
  • Page 32 400 MHz CPU, 4.0 MB E-Cache ODULE OMPONENT VERVIEW The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), (see Figure 1), consists of the following components: • UltraSPARC™-II CPU at 400 MHz • UltraSPARC-II Data Buffer (UDB-II) • 4.0 Megabyte E-cache, made up of eight (256K X 18) data SRAMs and one 128K X 36 Tag SRAM •...
  • Page 33 24 and page 25. UPA Interconnect The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), supports full master and slave functionality with a 128-bit data bus and a 16-bit error correction code (ECC).
  • Page 34 The JTAG TCK signal is distributed to UDB-II, SRAMs and the CPU. For additional information about the JTAG interface, see "JTAG Testability," on page 22, and "JTAG (IEEE 1149.1) Timing," on page 23. ™ -II CPU Module at 3.3V, and V DD_CORE Sun Microsystems, Inc at 2.6V. The V supplies the DD_CORE July 1999...
  • Page 35 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. July 1999 UltraSPARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache Name and Function Name and Function Sun Microsystems, Inc Advanced Version SME5224AUPA-400...
  • Page 36 POWER_OV Connected to GND via a 1180-ohm resistor. Sets overvoltage level for programmable supply. 1. The thermistor used on the module (SME5224AUPA-400) is manufactured by KOA. Operating at 47K the thermistor has KOA part number NT32BT473J. ™ -II CPU Module...
  • Page 37 The block diagram for the LVPECL clocks "Clock Signal Distribution," on page 10, illustrates a typical system clock distribution network. Each clock line is a parallel-terminated, dual trace LVPECL clock signal for the CPU, the UPA and the SRAM devices. July 1999 Sun Microsystems, Inc...
  • Page 38 FR4, PCB Dielectric. ™ -II CPU Module CPU_CLK Module Connector UDB-II UPA_CLK0 UDB-II UPA_CLK1 UPA_CLK Clock Buffer UPA_CLK2 UPA_CLKx Sun Microsystems, Inc Module Boundary SRAM SRAM SRAM SRAM SRAM Clock Buffer SRAM SRAM SRAM SRAM/TAG UltraSPARC-II UPA Device UPA Device...
  • Page 39 , except when the CPU is being re-cycled, at which time the V ground. 3.14 3.30 2.47 2.60 – – -0.3 – – – – – – – – – Sun Microsystems, Inc Advanced Version SME5224AUPA-400 Units Units 3.46 2.73 – + 0.2 – . See the section...
  • Page 40 , are respectively 3.30V and 2.6V. The estimated maximum power consumption of the DD_CORE UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module (SME5224AUPA-400) is 70 watts at 400 MHz. The estimated maximum power consumption includes the CPU, the SRAMs, the clock logic and the 8 watts consumed by the DC-DC regulator.
  • Page 41 3.1 nH Trace 3 1.0 pF 1.0 pF 7 pF Measure point for XB1 XB1 BGA Package Loading Measure point for CPU Sun Microsystems, Inc Advanced Version SME5224AUPA-400 Trace 4 via 0.6 pF 7 pF UDB-II of Second Module Package Loading...
  • Page 42 Setup Signals and Hold Time Signals UPA_DATA [127:0] Setup time UPA_ADDR [35:0] UPA_ADDR_VALID, UPA_REQ_IN [2:0], UPA_SC_REQ_IN, UPA_DATA_STALL, UPA_ECC_VALID, UPA_RESET_L, UPA_XIR_L UPA_ECC [15:0] UPA_S_REPLY [3:0] ™ -II CPU Module Waveforms Sun Microsystems, Inc 400 MHz CPU 100 MHz UPA Unit – – – – July 1999...
  • Page 43 2.4V Rising Edge Output 0.8V 0.4V 2.4V 2.0V Falling Edge Output 0.8V 0.4V Waveforms 2 Sun Microsystems, Inc Advanced Version SME5224AUPA-400 400 MHz CPU 100 MHz UPA Unit – – – – 400 MHz CPU 100 MHz UPA Unit –...
  • Page 44 ™ -II CPU Module Front SRAM Heat Sinks 6.250 [158.75] 5.890 [149.61] 0.112 [2.86 ] 2.551 [64.79] Dimensions: inches [millimeters] Sun Microsystems, Inc Module Ejectors CPU/Voltage Regulator Heat Sink Thermistor Location (RT0201) 0.179 [4.55] 3.680 [93.47] 0.570 [14.48] Pin 1 0.174 [4.41]...
  • Page 45 NOTE: A minimum backside clearance is required for airflow cooling of the backside heatsink. July 1999 UltraSPARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache Figure 8. CPU Module Side View Sun Microsystems, Inc Advanced Version SME5224AUPA-400 Module Shroud Bidirectional Airflow...
  • Page 46 In addition, the lower the junction temperature, the higher the system reliability. The CPU temperature must be verified under a range of system compute loads and system environmental conditions, using one of the temperature measuring methods described herein. ™ -II CPU Module Sun Microsystems, Inc July 1999...
  • Page 47 Accuracy of this value requires that good thermal contact is made between the package and the heatsink. This value is dependent on the heatsink design, the airflow direction, and the airflow velocity. The ducted airflow. Sun Microsystems, Inc Advanced Version SME5224AUPA-400...
  • Page 48 Airflow Bottomside 100 LFM @ 30 C up to 2,000 feet, altitude, maximum 150 LFM @ 40 C up to 10,000 feet, altitude, maximum ™ -II CPU Module 0.91 0.84 0.78 Sun Microsystems, Inc 1000 0.72 0.67 0.64 July 1999...
  • Page 49 If the heatsink temperature (Ts) is known then the following ther- mal equation can be used to estimate the junction temperature: Tj = Ts + [Pd ( jc + cs)] July 1999 Sun Microsystems, Inc...
  • Page 50 JTAG T ESTABILITY The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), implements the IEEE 1149.1 standard to aid in board level testing. Boundary Scan Description Language (BSDL) files are available for all the active devices on the module, except the clock buffer.
  • Page 51 In-Phase Out-of-Phase Figure 11. Voltage Waveforms - Propagation Delay Times July 1999 UltraSPARC ™ -II CPU Module 400 MHz CPU, 4.0 MB E-Cache Clock 2.0V 1.5V 1.5V Clock 2.0V 2.0V Output 0.8V Output 0.8V Sun Microsystems, Inc Advanced Version SME5224AUPA-400...
  • Page 52 UPA_DATA[34] UPA_DATA[32] UPA_DATA[22] UPA_DATA[20] UPA_DATA[18] UPA_DATA[16] UPA_DATA[6] UPA_DATA[4] UPA_DATA[2] (Pin 319) UPA_DATA[0] GND (Pin 320) GND (Pin 326) Sun Microsystems, Inc GND (Pin 5) GND (Pin 11) VDD_CORE VDD_CORE VDD_CORE VDD_CORE UPA_PORT_ID[1] VDD_CORE VDD_CORE GND (Pin 137) GND (Pin 143)
  • Page 53 UPA_DATA[40] UPA_DATA[30] UPA_DATA[28] UPA_DATA[26] UPA_DATA[24] UPA_DATA[14] UPA_DATA[12] UPA_DATA[10] UPA_DATA[8] (Pin 321) (Pin 320) GND UPA_CLK1_POS (Pin 327) (Pin 326) GND Sun Microsystems, Inc Advanced Version SME5224AUPA-400 UPA_ADDR[9] (Pin 6) UPA_ADDR[11] (Pin 12) UPA_ADDR[13] UPA_ADDR[15] UPA_ADDR[25] UPA_ADDR[27] UPA_ADDR[29] UPA_ADDR[31] UPA_ADDR_VALID UPA_REQ_IN[0]...
  • Page 54 SRAM heatsinks because this action can cause unseen damage to the solder connections. Always handle modules and other electronic devices in an ESD-controlled environment. ™ -II CPU Module Conditions Min. – – – Sun Microsystems, Inc Value Typ. Unit – – C/min. – inches –...
  • Page 55 Re-organization of the datasheet and update of specifications. New section concerning the System Timing and Thermal Specifications. Revised specifications for DC characteristics and module power consumption. Illustrations reflect a new heat sink design. Thermal section reflects the latest heatsink design. Sun Microsystems, Inc Advanced Version SME5224AUPA-400...
  • Page 56 Sun Microsystems, Inc. Sun, Sun Microsystems, the Sun Logo, Ultra, and VIS are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries.