Quectel EG91 Series Hardware Design page 48

Table 13:Logic Levels of Digital I/O
Parameter
V
IL
V
IH
V
OL
V
OH
The module provides 1.8V UART interfaces. A level translator should be used if customers' application is
equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments is
recommended. The following figure shows areference design.
Please visit http://www.ti.com formore information.
Another example with transistor translation circuit is shown as below. Thecircuitdesign of dotted line
section can refer to the circuitdesign of solid linesection, in terms of both module input and output circuit
design. Please pay attention to the direction of connection.
EG91_Hardware_Design
Min.
-0.3
1.2
0
1.35
Figure 20: Reference Circuit with Translator Chip
Max.
0.6
2.0
0.45
1.8
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LTE Module Series
EG91 Hardware Design
Unit
V
V
V
V