Uart Interfaces - Quectel EG91 Series Hardware Design

The module provides two UART interfaces: the main UART interface and thedebug UART interface. The
following shows their features.
 The main UART interface supports 9600bps, 19200bps, 38400bps, 57600bps, 115200bps,
230400bps, 460800bps, 921600bps and 3000000bps baud rates, and the default is 115200bps. It
supports RTS and CTS hardware flow control, and is used for AT command communication only.
 The debug UART interface supports 115200bpsbaud rate. It is used forLinux console and log output.
The following tables show the pin definition of the two UART interfaces.
Table 11: Pin Definition of Main UART Interfaces
Pin Name Pin No.
RI 39
DCD 38
CTS 36
RTS 37
DTR 30
TXD 35
RXD 34
Table 12: Pin Definition of Debug UART Interface
Pin Name Pin No.
DBG_TXD 23
DBG_RXD 22
The logic levels are described in the following table.
EG91_Hardware_Design

3.11. UART Interfaces

I/O Description
DO Ring indicator
DO Data carrier detection
DO Clear to send
DI Request to send
DI Sleep mode control
DO Transmit data
DI Receive data
I/O Description
DO Transmit data
DI Receive data
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LTE Module Series
EG91 Hardware Design
Comment
1.8V power domain
Comment
1.8V power domain
1.8V power domain