abov MC96F8204M Core Microcontrollers Manuals

Manuals and User Guides for abov MC96F8204M Core Microcontrollers. We have 1 abov MC96F8204M Core Microcontrollers manual available for free PDF download: User Manual

abov MC96F8204M User Manual

abov MC96F8204M User Manual (212 pages)

CMOS single-chip 8-bit MCU with 12-bit A/D converter

Brand: abov | Category: Microcontrollers | Size: 2 MB

Table of Contents

Table of Contents

40
- Revision History
  2
- Overview
  3
- Description
  3
- Features
  4
- Development Tools
  5
- Compiler
  5
- Ocd(On-Chip Debugger) Emulator and Debugger
  5
- Programmer
  6
- MTP Programming
  8
- Overview
  8
- On-Board Programming
  8
- Circuit Design Guide
  9
- Block Diagram
  10
- Pin Assignment
  11
- Package Diagram
  13
- Pin Description
  18
- Port Structures
  20
- General Purpose I/O Port
  20
- External Interrupt I/O Port
  21
- Electrical Characteristics
  22
- Absolute Maximum Ratings
  22
- Recommended Operating Conditions
  22
- A/D Converter Characteristics
  23
- Power-On Reset Characteristics
  23
- Low Voltage Reset and Low Voltage Indicator Characteristics
  24
- High Frequency Internal RC Oscillator Characteristics
  25
- Low Frequency Internal RC Oscillator Characteristics
  25
- Internal Watch-Dog Timer RC Oscillator Characteristics
  25
- DC Characteristics
  26
- AC Characteristics
  27
- SPI Characteristics
  28
- UART Characteristics
  29
- I2C Characteristics
  30
- Data Retention Voltage in Stop Mode
  31
- Internal Flash Rom Characteristics
  32
- Input/Output Capacitance
  32
- Main Clock Oscillator Characteristics
  33
- Sub Clock Oscillator Characteristics
  34
- Main Oscillation Stabilization Characteristics
  35
- Sub Oscillation Characteristics
  35
- Operating Voltage Range
  36
- Recommended Circuit and Layout
  37
- Recommended Circuit and Layout with SMPS Power
  38
- Lfirc
  39
  - Table of Contents
    40
  - Memory
    43
    
    Program Memory
    43
    
    Data Memory
    45
    
    Register Bank
    45
    
    Extended SFR Area
    47
    
    SFR Map
    48
    
    SFR Map Summary
    48
    
    Extended SFR Map Summary
    49
    
    SFR Map
    50
- Typical Characteristics
  39
- X-Tal
  51
- Lfirc
  52
  - Extended SFR Map
    54
    
    SFR Map
    55
  - O Ports
    57
    
    Data Register (Px)
    57
    
    De-Bounce Enable Register (P0DB)
    57
    
    Direction Register (Pxio)
    57
    
    I/O Ports
    57
    
    Open-Drain Selection Register (Pxod)
    57
    
    Port Function Selection Register (P0FSRH, P0FSRM, P0FSRL, P1FSR)
    57
    
    Port Register
    57
    
    Pull-Up Resistor Selection Register (Pxpu)
    57
    
    Register Map
    58
    
    P0 Port
    59
    
    P0 Port Description
    59
    
    Register Description for P0
    59
    
    P1 Port
    64
    
    P1 Port Description
    64
    
    Register Description for P1
    64
    
    P2 Port
    66
    
    P2 Port Description
    66
    
    Register Description for P2
    66
  - Interrupt Controller
    67
    
    Overview
    67
    
    External Interrupt
    69
    
    Block Diagram
    70
    
    Interrupt Vector Table
    71
    
    Interrupt Sequence
    72
    
    Effective Timing after Controlling Interrupt Bit
    73
    
    Multi Interrupt
    74
    
    Interrupt Enable Accept Timing
    75
    
    Interrupt Service Routine Address
    75
    
    Saving/Restore General-Purpose Registers
    75
    
    Interrupt Timing
    76
    
    External Interrupt Flag Register (EIFLAG)
    77
    
    External Interrupt Polarity Register (EIPOL0, EIPOL1)
    77
    
    Interrupt Enable Register (IE, IE1, IE2, IE3)
    77
    
    Interrupt Priority Register (IP, IP1)
    77
    
    Interrupt Register Overview
    77
    
    Register Map
    77
    
    Interrupt Register Description
    78
    
    Register Description for Interrupt
    78
  - Peripheral Hardware
    83
    
    Clock Generator
    83
    
    Overview
    83
    
    Block Diagram
    84
- Lfirc
  84
  - Register Map
    85
    
    Clock Generator Register Description
    85
    
    Register Description for Clock Generator
    85
- X-Tal
  85
  - Basic Interval Timer
    88
    
    Block Diagram
    88
    
    Overview
    88
    
    Register Map
    88
    
    Basic Interval Timer Register Description
    89
    
    Register Description for Basic Interval Timer
    89
    
    Overview
    90
    
    Watch Dog Timer
    90
    
    WDT Interrupt Timing Waveform
    90
    
    Block Diagram
    91
    
    Register Map
    91
    
    Watch Dog Timer Register Description
    91
    
    Register Description for Watch Dog Timer
    92
  - Watch Timer
    93
    
    Block Diagram
    93
    
    Overview
    93
    
    Register Description for Watch Timer
    94
    
    Register Map
    94
    
    Watch Timer Register Description
    94
  - Timer 0
    96
    
    Overview
    96
    
    8-Bit Timer/Counter Mode
    97
    
    8-Bit Capture Mode
    98
    
    Block Diagram
    100
    
    Register Map
    100
    
    Timer/Counter 0 Register Description
    100
    
    Register Description for Timer/Counter 0
    101
  - Timer 1/2
    103
    
    16-Bit Timer/Counter Mode
    103
    
    Overview
    103
    
    16-Bit Capture Mode
    105
    
    16-Bit PPG Mode
    107
    
    Block Diagram
    109
    
    Register Map
    109
    
    Register Description for Timer/Counter 1/2
    110
    
    Timer/Counter 1/2 Register Description
    110
  - 12-Bit A/D Converter
    113
    
    Conversion Timing
    113
    
    Overview
    113
    
    Block Diagram
    114
    
    ADC Operation
    115
    
    ADC Register Description
    117
    
    Register Map
    117
    
    Register Description for ADC
    118
  - Usart
    121
    
    Overview
    121
    
    UART Block Diagram
    122
    
    USART Clock Generation
    123
    
    External Clock (SCK)
    124
    
    Synchronous Mode Operation
    124
    
    UART Data Format
    125
    
    UART Parity Bit
    126
    
    UART Sending TX Data
    126
    
    UART Transmitter
    126
    
    UART Transmitter Flag and Interrupt
    126
    
    UART Disabling Transmitter
    127
    
    UART Parity Generator
    127
    
    UART Receiver
    127
    
    UART Receiving RX Data
    127
    
    UART Disabling Receiver
    128
    
    UART Parity Checker
    128
    
    UART Receiver Flag and Interrupt
    128
    
    Asynchronous Data Reception
    129
    
    SPI Clock Formats and Timing
    131
    
    SPI Mode
    131
    
    USART SPI Block Diagram
    134
    
    Register Description for USART
    135
    
    Register Map
    135
    
    USART Register Description
    135
    
    Block Diagram
    140
    
    Overview
    140
    
    I2C Bit Transfer
    141
    
    Start / Repeated Start / Stop
    141
    
    Data Transfer
    142
    
    I2C Acknowledge
    143
    
    Synchronization / Arbitration
    144
    
    Master Transmitter
    145
    
    Operation
    145
    
    Master Receiver
    147
    
    I2C Slave Transmitter
    149
    
    Slave Receiver
    150
    
    I2C Register Description
    151
    
    Register Map
    151
    
    Register Description for I2C
    152
    
    FLASH Crc/Checksum Generator
    156
    
    Overview
    156
    
    Block Diagram
    161
    
    Register Map
    161
    
    Flash CRC Generator Register Description
    162
    
    Register Description for Flash CRC Generator
    162
  - Power down Operation
    165
    
    Overview
    165
    
    Peripheral Operation in IDLE/STOP Mode
    165
    
    IDLE Mode
    166
    
    STOP Mode
    167
    
    Release Operation of STOP Mode
    168
    
    Power down Operation Register Description
    169
    
    Register Description for Power down Operation
    169
    
    Register Map
    169
  - Reset
    170
    
    Overview
    170
    
    RESET Block Diagram
    170
    
    Reset Source
    170
    
    Power on RESET
    171
    
    RESET Noise Canceller
    171
    
    External RESETB Input
    174
    
    Brown out Detector Processor
    175
    
    LVI Block Diagram
    177
    
    Register Map
    177
    
    Reset Operation Register Description
    177
    
    Register Description for Reset Operation
    178
  - On-Chip Debug System
    181
    
    Description
    181
    
    Overview
    181
    
    Feature
    182
    
    Basic Transmission Packet
    183
    
    Two-Pin External Interface
    183
    
    Bit Transfer
    184
    
    Data Transfer
    184
    
    Packet Transmission Timing
    184
    
    Acknowledge Bit
    185
    
    Start and Stop Condition
    185
    
    Connection of Transmission
    186
  - Flash Memory
    187
    
    Description
    187
    
    Overview
    187
    
    Flash Program ROM Structure
    188
    
    Register Description for Flash Memory Control and Status
    189
    
    Register Map
    189
    
    Register Description for Flash
    190
    
    Protection Area (User Program Mode)
    192
    
    Serial In-System Program (ISP) Mode
    192
    
    Erase Mode
    193
    
    Write Mode
    194
    
    Protection for Invalid Erase/Write
    196
    
    Flow of Protection for Invalid Erase/Write
    198
    
    Code Write Protection Mode
    199
    
    Read Mode
    199
  - Configure Option
    200
    
    Configure Option Control
    200
  - Appendix
    201
    
    Instruction Table
    201
    
    Flash Protection for Invalid Erase/Write
    205
Table of Contents

208

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