Table 4.2. Device Power Rail Summary And Test Points - Lattice CrossLink LIF-MD6000 Master Link Board - Revision C User Manual

Table 4.2. Device Power Rail Summary and Test Points

Voltage Rail
12 V
5 V
+3.3 V
+2.5 V
+1.8 V
+1.2 V
VCC_CORE
VCCIO0
VCCIO1
VCCIO2
VCC_DPHY
1K_VCC_CORE
1K_VCCIO0
1K_VCCIO1
1K_VCCIO2
1K_VCCIO3
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FPGA-EB-02018-1.0
Source Rail
—
12 V
5 V
5 V
5 V
5 V
+1.2 V
+2.5 V / +3.3 V
+1.2 V / +2.5 V / +3.3 V
+1.2 V / +2.5 V / +3.3 V
+1.2 V
+1.2 V
+2.5 V / +3.3 V
+2.5 V / +3.3 V
+2.5 V / +3.3 V
+2.5 V / +3.3 V
CrossLink LIF-MD6000 Master Link Board - Revision C
Current Sense Resistor
—
—
—
—
—
—
R19
R20 / R24
R21 / R25 / R434 / R448
R28 / R33 / R435 / R449
R417
R190
R410 / R411
R184 / R185
R186 / R187
R188 / R189
Evaluation Board User Guide
Test Points
12V0
5V0
3V3
2V5
—
1V2
VCC_CORE1
VCCIO0
VCCIO1
VCCIO2
VCC_DPHY
1K_VCC_CORE1
1K_VCCIO0
1K_VCCIO1
1K_VCCIO2
1K_VCCIO3
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