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CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
5
NOTE : INPUT VOLTAGE SHOULD BE 12V AT 3A Max
J3
U3
1
1
2
1
2
3
R22
R144
FUSE
C130
C123
4.7k
4.7k
D
2
10uF
0.1uF
DNI
PJ-032A
GND3
NOTE : Place this gnd test point near J3
5V
500mA traces
U15
500mA traces
R165
0
10uF
0.1uF
1
2
IN
OUT
C94
C95
AP7313-12SAG-7
C
5V
500mA traces
U5
R36
3
2
IN
OUT
4
TAB
1K
D3
C20
GND
Green
10uF
1
NCP1117ST33T3G
VCC_2.5V
5V
500mA traces
U6
R39
0
3
2
B
IN
OUT
4
TAB
C23
C24
GND
10uF
22uF
1
NCP1117ST25T3G
VCC_1.8V
5V
500mA traces
U17
R192
0
3
2
IN
OUT
4
TAB
C114
GND
A
C113
10uF
1
NCP1117ST18T3G
22uF
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
4
12V
J8
5V_INT
D1
1
2
5V_SW
SL44-E3/57T
VBUS_5V
D14
1
2
2 Position Terminal Block_0
DNI
SL44-E3/57T
J9
VCC_1.2V
+1.2V
L4
10uF
0.1uF
2
1
600ohm 500mA
C96
C97
2 Position Terminal Block_0
VCC_3.3V
+3.3V
R37
0
L5
2
1
R233
600ohm 500mA
470E
C21
D25
R499
Green
22uF
1K
+2.5V
5V_SW
L6
2
1
600ohm 500mA
12V
C115
10uF
+1.8V
L7
2
1
600ohm 500mA
R229
15K
ON BOARD POWER REGULATORS
C127
680pF
4
Power Regulator Interface
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
12V
J24
+1.2V
2V5
R434
1
4
1V2
VCCIO1/2
1
1
3V3
2
Tri-Con
2
Snow Voltage
Selection
J25
5V_INT
+1.2V
2V5
R435
1
4
1V2
VCCIO1/2
1
1
3V3
Tri-Con
2
2
+1.2V
1K_VCC_CORE
+3.3V
R190
1
1K_VCC_CORE1
+2.5V
1K_VCC_CORE
XO3-1K Voltage
Selection
5V
SW1
PWR
GLOBAL POWER TEST POINTS
0.1uF
12V0
1V2
C29
12V
+1.2V
U18
LT3680
4
1
VIN
BD
5
R231
RUN_SS
536K
9
VC
8
R232
FB
100K
10
2
RT
BOOST
C128
7
PG
0.47uF
3
R230
SW
6
34K
SYNC
11
EPAD
D12
LT3680
MBRA340T3G
Manufacturer = Linear
0.3VF
PART_NUMBER = LT3680EDD#PBF
3
2
+1.2V
VCC_CORE
+3.3V
1
1
R25
+2.5V
1
2
R448
VCCIO1
1
R19
1
R20
3
R21
+3.3V
VCC_CORE1
+2.5V
VCC_CORE
R24
1
DNI
1
R33
+2.5V
1
2
R449
VCCIO2
VCCIO0
1
3
R28
+3.3V
VCCIO0
VCCIO1
1K_VCCIO0
+3.3V
1K_VCCIO1
+3.3V
1K_VCCIO2
R410
1
R184
1
R186
1
+2.5V
+2.5V
R411
1
R185
1
R187
1
DNI
DNI
DNI
1K_VCCIO0
1K_VCCIO1
1K_VCCIO2
1K_VCCIO0
1K_VCCIO1
1K_VCCIO2
2V5
3V3
+2.5V
+3.3V
5V
5V_INT
C129
47uF
L8
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
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4.7uH
Title
Title
Title
POWER REGULATOR I/F
POWER REGULATOR I/F
POWER REGULATOR I/F
Size
Size
Size
Project
Project
Project
B
B
B
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
Date:
Date:
Date:
28-Mar-17
28-Mar-17
28-Mar-17
2
1
VCCIO0
+1.2V
VCC_DPHY
1
R417
1
VCC_DPHY1
D
VCC_DPHY
1
VCCIO1
VCCIO2
VCCIO2
+3.3V
1K_VCCIO3
C
R188
1
+2.5V
R189
1
DNI
1K_VCCIO3
1K_VCCIO3
B
5V0
GND2
GND1
GND4
GND5
A
Schematic Rev
Schematic Rev
Schematic Rev
1.0
1.0
1.0
Board Rev
Board Rev
Board Rev
1
1
1
Sheet
Sheet
Sheet
3
3
3
of
of
of
8
8
8
1
FPGA-EB-02018-1.0
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