Transmit Eye Diagram Setup Requirements; Transmit Eye Diagram Test Procedures (Sonet Scrambled Data Eye) - Lattice ORCA ORSO42G5 Technical Note

Evaluating with the high-speed serdes board
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Lattice Semiconductor

Transmit Eye Diagram Setup Requirements

You will need the following to complete this evaluation:
• ORSO42G5 High-Speed SERDES Board configured as described earlier.
• Orso4_felb6.bit bitstream and bitstream programming devices (ispDOWNLOAD cable and ispVM running
on a PC).
• ORCAstra GUI application and tx_eye.fpm macro.
• Scope to view data eye and high speed SMA cables (50Ω up to 3.0Gb/s) with bias tees at the input to the
scope.
• Clock source capable of driving a CML input clock (77.76-155.52MHz) and SMA cables from the clock
source to the Lattice High-Speed SERDES Board and to the trigger input of the scope. (Note: The eye mea-
surements could alternately be made using a Serial Data Analyzer. In that case no trigger connection is
required.)
• 5V DC wall power supply.
• 1.5V DC supply for the bias tees
A typical setup is shown in Figure 4.
Figure 4. Transmit Eye Diagram Setup
5V DC 4A
Power Supply
High-Speed SERDES Board
ispDOWNLOAD
Interface Cable
Cable
Computer

Transmit Eye Diagram Test Procedures (SONET Scrambled Data Eye)

1. Connect the system as shown in Figure 4. The scope SMA cables should be connected to the
HDOUTP_Bx and HDOUTN_Bx SMA connectors on the board.
2. Power-up the system
3. Start the clock generator and provide a nominal 155.52MHz CML reference clock.
4. Download the orso4_felb6.bit bitstream into the ORSO42G5.
5. Run the tx_eye.fpm macro using the pull-down menu in the ORCAstra application. This macro will set up
the AC and AD channels in a SONET AUTO_TOH transmit mode using the SONET scrambler.
6. Observe the SONET scrambled data eye on the scope.
ORSO42G5
DUT
HDOUTP_Bx
HDOUTN_Bx
REFCLKN_B
REFCLKP_B
ORCAstra
-
+
Agilent 81130A
Clock Source
(or equivalent)
Evaluating the ORCA ORSO42G5 with the
Agilent 86100B DCA
Agilent 816112
(or equivalent)
Electrical
Module
(or equivalent)
Picosecond
Picosecond
5575A
5575A
Bias Tee
Bias Tee
1.5V DC 0.5A
Power Supply
High = 500mV
Low = 0V
155MHz
4
High-Speed SERDES Board
20GHz
Trigger In
Note: Do not use
stand-alone bias tees
on channels (AA and BA).
Those channels have a
built-in bias tee.

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