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CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
5
1K_VCCIO0
U19A
D6
VCCIO0
C145
C143
10uF
0.1uF
D
C
LCMXO3LF-1300E-5MG121C
1K_VCCIO1
U19B
H5
VCCIO1
C153
C151
10uF
0.1uF
BANK1
PR5D/PCLKC1_0
B
PR5C/PCLKT1_0
NOTE : PLACE SWITCH IN THE TOP SIDE
VCCIO0
R440
LCMXO3LF-1300E-5MG121C
SW3
4.7k
TL1015AF160QG
XO3_RESET
A
100E
R487
C182
R488
1uF
47K
XO3 RESET
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
4
1K_VCCIO2
A10
PT9A
A2
BANK0
PT17A
A3
PT16A
A4
PT15A
A5
0
R452
SCL
PT12C/SCL/PCLKTO_0
SCL
{4,6}
A6
12MHZ
{2}
PT12B/PCLKC0_1
A7
PT11A
A8
PT10D/TDI
TDI
{2}
A9
PT10A
XO3_RESET
B2
PT17B
B3
PT16B
B4
PT15B
B5
0
R451
SDA
R403
SDA
{4,6}
PT12D/SDA/PCLKC0_0
B6
PT12A/PCLKTO_1
B7
PT11B
B8
PT10B
B9
4.7k
PT9B
C3
INITN
PT17C/INITN
C4
PROGRAMN
PT15D/PROGRAMN
C5
JTAGENB
PT15C/JTAGENB
C6
PT11D/TMS
TMS {2}
C7
TCK
{2}
PT11C/TCK
C8
PT9C
D4
DONE
PT17D/DONE
D7
PT10C/TDO
TDO
{2}
I/O Expander - I2C Muxing
1K_VCCIO3
B1
PR2C
C1
C141
C142
PR2D
C2
PR2A
D1
10uF
0.1uF
PR3B
D2
PR3A
D3
PR2B
E1
PR4D
E2
PR4C
E3
PR4B
E4
PR4A
F1
F2
F3
PR5A
1K_VCC_CORE
F4
PR5B
G1
PR8A
G2
U19E
PR8B
G3
D5
A1
PR8C
VCC
GND
G4
E5
A11
PR8D
VCC
GND
H1
F7
E6
PR9A
VCC
GND
H2
G7
E7
PR9B
VCC
GND
H3
F5
PR9C
GND
H4
F6
PR9D
GND
J1
G5
PR10A
GND
J2
G6
PR10C
GND
J3
L1
PR10D
GND
K1
L11
PR10B
GND
LCMXO3LF-1300E-5MG121C
1K_VCC_CORE
PLACE DECOUPLING CAPACITORS CLOSE TO THE U19 POWER PINS
C107
C106
C104
C105
10uF
0.1uF
0.1uF
0.1uF
4
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
U19C
H6
VCCIO2
PB6D/SO/SPISO
PB4A
C150
C147
PB18D
BANK2
PB18C
10uF
0.1uF
PB15C
PB11D
PB6C/MCLK/CCLK
PB4B
PB4C/CSSPIN
PB20D/SI/SISPI
1K_VCCIO0
PB20B
PB18B
PB15B
PB11B/PCLKC2_1
R404
R405
PB9B/PCLKC2_0
PB9C
PB6A
J32
PB4D
4.7k
4.7k
PB20C/SN
3
PB20A
2
PB18A
1
PB15A
PB11A/PCLKT2_1
CON3
PB9A/PCLKT2_0
PB9D
PB6B
LCMXO3LF-1300E-5MG121C
U19D
D8
B10
VCCIO3
PL2C/L_GPLLT_IN
F8
B11
VCCIO3
PL2D/L_GPLLC_IN
C139
C140
H8
C10
VCCIO3
PL3A/PCLKT3_2
C11
PL3B/PCLKC3_2
0.1uF
0.1uF
C9
PL2A/L_GPLLT_FB
D10
PL4A
D11
PL4B
D9
PL3C
BANK3
E10
PL4C
E11
PL4D
E8
PL2B/L_GPLLC_FB
E9
PL3D
F10
PL5B/PCLKC3_1
F11
PL5A/PCLKT3_1
F9
PL5C
G10
PL8B
G11
PL8A
G8
PL8D
G9
PL8C
H10
PL9B/PCLKC3_0
H11
PL9A/PCLKT3_0
J10
PL10D
J11
PL10A
K11
PL10C
LCMXO3LF-1300E-5MG121C
DEBUG1
DEBUG2
DEBUG3
C102
DEBUG4
0.1uF
3
2
I
C Expander
2
XO3_SPISO
1K_VCCIO2
H7
H9
J4
J5
J6
J7
R176
R175
R178
R177
R477
R478
R480
R479
XO3_SPICLK
J8
J9
K10
XO3_SPISI
K2
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
K3
K4
K5
SDA1
{5}
K6
Red
SCL1
{5}
K7
D23
SCL2
{5}
K8
SDA2
{5}
K9
L10
L2
XO3_SPICS
L3
L4
L5
SDA3
{5}
L6
SCL3
{5}
L7
SCL4
{5}
L8
SDA4
{5}
L9
1K_VCCIO2
R485
R486
1K_VCCIO2
1K_VCCIO0
J31
4.7k
4.7k
1
2
XO3_SPISO
3
4
SDA
XO3_SPISI
5
6
SCL
XO3_SPICLK
7
8
DONE
XO3_SPICS
9
10
HEADER 5X2
DEBUG1
DEBUG2
DEBUG3
DEBUG4
LED1
D30
LED2
R436
470E
blue
LED3
LED1
1
LED4
D31
R437
470E
blue
1K_VCCIO3
LED2
1
D32
R438
470E
blue
LED3
1
R483
R484
D33
R439
470E
blue
LED4
1
4.7k
4.7k
XO3_SCL
{4}
XO3_SDA {4}
J23
1
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
2
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
3
4
Title
Title
Title
I2C Expander
I2C Expander
I2C Expander
4 HEADER
Size
Size
Size
Project
Project
Project
B
B
B
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
Date:
Date:
Date:
28-Mar-17
28-Mar-17
28-Mar-17
2
1
1K_VCCIO0
R500
680R
D
DONE
C
2
2
B
2
2
A
Schematic Rev
Schematic Rev
Schematic Rev
1.0
1.0
1.0
Board Rev
Board Rev
Board Rev
1
1
1
Sheet
Sheet
Sheet
7
7
7
of
of
of
8
8
8
1
FPGA-EB-02018-1.0
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