Lattice ORCA ORSO42G5 Technical Note

Evaluating with the high-speed serdes board

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April 2004

Introduction

Contained in this package is information that will assist you in evaluating and verifying your ORCA

designs using the Lattice High-Speed SERDES Board and the ORCAstra system bus control panel (available for

download from the Lattice web site at www.latticesemi.com/products/devtools/software/orcastra/index.cfm).

The Lattice High-Speed SERDES Board supports a number of testing and evaluation setups for both the

ORT42G5 and the ORSO42G5. This document will cover some common types of evaluation testing that can be

performed on the ORSO42G5 device in SERDES-only and SONET modes. The tests include transmitter eye dia-

gram measurement, SONET Near-end Loop-back and SERDES-only, SONET and Aligned SONET Far-end Loop-

back. All of the described evaluation setups use the orso4_felb6.bit bitstream. This bitstream is included with the

package you have downloaded from the Lattice web site at www.latticesemi.com/products/devtools/hard-

ware/orso42g5-board/index.cfm. A unique ORCAstra macro is used to conﬁgure the device for each test.

PC and Evaluation Board Setup

This document assumes the ORCAstra application and bitstream programming software (ispVM

the user's PC. It also assumes the baseline board conﬁguration listed below. (The user is also encouraged to

experiment with other conﬁgurations.)

• All jumpers should be in their default position and default programming in the ispPAC

described in the Evaluation Board User Manual. This will apply power in the recommended sequence and

provide 3.3V V

DDIO

• ispDOWNLOAD

tor on the board (J30). The pDS4102-DL2 is included with the Lattice High-Speed SERDES Board. Alter-

nately, a HW-USB-1A ispDOWNLOAD cable can be used.)

• ORCAstra connected to the parallel or USB port on the PC and the ORCAstra Interface DB-25 or USB con-

nector on the board (J108).

• External differential clock connected to the External System Clock SMA connectors (J87/J88 and J84/J85).

• External power should be provided from the Molex cable and power module.

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Summary of Contents for Lattice ORCA ORSO42G5

Page 1: Recommended Reading
Contained in this package is information that will assist you in evaluating and verifying your ORCA ORSO42G5 designs using the Lattice High-Speed SERDES Board and the ORCAstra system bus control panel (available for download from the Lattice web site at www.latticesemi.com/products/devtools/software/orcastra/index.cfm).
Page 2: Orso4_Felb6 Bitstream
Evaluating the ORCA ORSO42G5 with the Lattice Semiconductor High-Speed SERDES Board Figure 1. Near-end Loop-back ORSO42G5 Serial Data FPGA SERDES 32-bit Data Reference Clock Far-end Loop-back (FELB) is deﬁned as the data path from the SERDES input, to parallel data and back out the SERDES as shown in Figure 2.
Page 3: Transmit Eye Diagram
SERDES-only mode or the SONET mode. Transmit Eye Diagram One of the most fundamental evaluations that can be performed with the Lattice High-Speed SERDES Board is observation and measurement of the data eye generated by the device. The ORSO42G5 device’s major mode will produce a SONET scrambled data eye.
Page 4: Transmit Eye Diagram Setup Requirements
• Clock source capable of driving a CML input clock (77.76-155.52MHz) and SMA cables from the clock source to the Lattice High-Speed SERDES Board and to the trigger input of the scope. (Note: The eye mea- surements could alternately be made using a Serial Data Analyzer. In that case no trigger connection is required.)
Page 5: Near-End Loop-Back
Evaluating the ORCA ORSO42G5 with the Lattice Semiconductor High-Speed SERDES Board Now that the eye is present, the system can be manipulated to improve and/or distort the eye diagram. The ORCAstra software can be used to change the pre-emphasis settings for the CML output buffer, change the half- amplitude setting for the CML output buffer, change the half-rate setting for the Tx SERDES channel, or change the frequency of the incoming reference clock.
Page 6: Sonet Tests
Evaluating the ORCA ORSO42G5 with the Lattice Semiconductor High-Speed SERDES Board PRBS 2 -1 sequences to test the ORSO42G5 device. Different types of transmit data eyes can also be observed and measured using different data patterns in this mode. SONET Tests The active blocks in the SONET data path are shown in Figure 6.
Page 7: Setup Requirements: Far-End Loop-Back Testing
Evaluating the ORCA ORSO42G5 with the Lattice Semiconductor High-Speed SERDES Board Figure 7. Aligned SONET Data Path (orso4_felb6.bit, Channel AC and AD) FPGA ASIC HDIN_A FIFO Rx SONET Rx SERDES 32-Bit Data DOUTAx_FP RWCKAx HDOUT_Ax Tx SONET Tx SERDES TSYSCLKAx TCK78A (Derived from REFCLK) Serial data is input through the CML buffer into the SERDES.
Page 8: Test Procedures
Evaluating the ORCA ORSO42G5 with the Lattice Semiconductor High-Speed SERDES Board Figure 8. Far-end Loop-back Test Setup 5V DC 4A Power Supply High-Speed SERDES Board HDINP_A/Bx Data Source HDINN_A/Bx (Typically a BERT with ORSO42G5 HDOUTP_A/Bx 8b/10b capability) HDOUTN_A/Bx Ext. Clock...
Page 9: Aligned Sonet Felb
Evaluating the ORCA ORSO42G5 with the Lattice Semiconductor High-Speed SERDES Board Aligned SONET FELB 1. Connect the system as shown in Figure 8. The data SMA cables should be connected to the HDIN_Ax and HDOUTN_Ax SMA connectors on the board.
Page 10: Appendix A. Function Of The Bias Tee Network
The FPSC 2.5/3.125G SERDES high speed outputs are designed to operate into 50Ω termination impedance biased at 1.5V or 1.8V DC. (This is the internal termination provided by Lattice 2.5/3.125G SERDES inputs and other vendor CML inputs.) Since most oscilloscopes and Digital Communications Analyzers (DCAs) have 50Ω...
Page 11 Not all bias tees are the same. There are a variety of bias tees designed for speciﬁc frequency ranges and DC cur- rent levels, from several different vendors. Lattice uses a Picosecond Pulse Lab bias tee. More detailed character- ization and application documents are available from this vendor. See the References section at the end of this document.
Page 12 Evaluating the ORCA ORSO42G5 with the Lattice Semiconductor High-Speed SERDES Board 2. Some newer test equipment provides adjustable bias voltage on the internal 50Ω input terminations. This equipment may be directly connected to the SERDES Tx output, as shown below.