Lattice CrossLink LIF-MD6000 Master Link Board - Revision C User Manual page 3

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
Figures
Figure 1.1. Top View of Master Link Board and its Key Components ................................................................................... 6
Figure 1.2. Bottom View of Master Link Board..................................................................................................................... 6
Figure 3.1. Programming Block ............................................................................................................................................. 8
Figure 3.2. Bridging Block ..................................................................................................................................................... 9
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Figure 3.3. I C Expander Block .............................................................................................................................................. 9
Figure 4.1. Power Supply Block........................................................................................................................................... 10
Figure 6.1. Top View of SMA IO Link Board ........................................................................................................................ 14
Figure 6.2. Bottom View of SMA IO Link Board .................................................................................................................. 14
Figure 7.1. Top View of Breakout IO Link Board ................................................................................................................. 17
Figure 7.2. Bottom View of Breakout IO Link Board ........................................................................................................... 17
Tables
Table 2.1. Headers and Test Connectors .............................................................................................................................. 7
Table 4.1. Power LEDs ........................................................................................................................................................ 10
Table 4.2. Device Power Rail Summary and Test Points ..................................................................................................... 11
Table 5.1. Status LED I/O Map ............................................................................................................................................ 12
Table 6.1. Headers and Test Connectors ............................................................................................................................ 13
Table 6.2. U1 Connector Description .................................................................................................................................. 13
Table 7.1. Headers and Test Connectors ............................................................................................................................ 15
Table 7.2. U1 Connector Description .................................................................................................................................. 15
Table 7.3. J2 Header Description ........................................................................................................................................ 16
Table 8.1. Ordering Information ......................................................................................................................................... 18
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 3