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5
SW5
TL1015AF160QG
WAKE_UP
U8A
J2
0
R415
PB47/PCLKT0_0/USER_SDA
D
H2
CDONE/PB49/PMU_WKUPN
F2
0
R416
PB48/PCLKT0_1/USER_SCL
F1
PB50/MOSI
J1
PB51/MISO
G1
PB52/SPI_SS/CSN/SCL
H1
PB53/SPI_SCK/MCK/SDA
G2
CRESET_B
G3
VCCIO0
USB_SDA
USB_SCL
LIF-MD6000-6MG81I
CON3
J36
VCCIO0
NOTE : PLACE SWITCH IN THE TOP SIDE
R131
C
SW2
TL1015AF160QG
4.7k
100E
SYS_RST
CRESETB
R489
C183
R490
1uF
47K
CRESETb
12V
CRESETB
5V
R78
R441
B
R442
10K
3K
1K
D26
D27
Green
Green
+1.2V
Q9
1
MMBT2222A
R395
10K
A
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0
4
VCCIO0
CLK_SDA
CDONE
SDA
CDONE
{2}
{4,7}
SDA
CLK_SCL
SISPI
SISPI
{2,4,5,6}
SPISO
SPISO
{2,4,5,6}
CSSPIN
CSSPIN
{2,4,5,6}
30E
R83
MCLK
MCLK
{2,6}
CRESETB
CRESETB
{2}
NOTE : PLACE R83 Close to U8 device
VCCIO0
SCL
C176
C202
{4,7}
SCL
100nF
10uF
16V
CON3
VCCIO2
J35
PLACE CLOSE TO U8
J4
C98
CLK_EXT
2
1
0
R183
3
J7
100nF
4
50 Ohm Clock Route
10V
1
5
2
73391-0060
J22
CON2
CLK_EXT_REF
VCCIO2
2
1
0
R433
3
4
50 Ohm Clock Route
5
73391-0060
C179
PLACE CLOSE TO U8
100nF
10V
5V
5V
R443
R444
1K
1K
D28
D29
Green
Green
+1.8V
Q10
1
Q11
1
MMBT2222A
R399
10K
MMBT2222A
R400
4
Bank0, Flash Interface
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
R76
R77
2K
2K
J26
1
CLK_INT
In1
4
2
CLK_SDA
In3
Out
{2}
USB_SDA
3
CLK_EXT
In2
{2}
USB_SCL
Tri-Con
{2,4,5,6}
{2,6}
J27
1
CLK_INT_REF
In1
{2,4,5,6}
CSSPIN
4
2
CLK_SCL
In3
Out
3
CLK_EXT_REF
In2
Tri-Con
OSCILLATOR
R160
X3
100K
4
1
NOTE : PLACE X3 NEAR U8
VDD
STDBY#
NOTE : R159 SHUOULD BE PLACED
NEAR X3
2
3
CLK_INT
0
GND
OUT
R159
KC3225A27.0000C30E0A
OSCILLATOR
R432
NOTE : PLACE X4 NEAR U8
X4
100K
4
1
NOTE : R431 SHUOULD BE PLACED
VDD
STDBY#
NEAR X4
R431
2
3
0
CLK_INT_REF
GND
OUT
KC3225A27.0000C30E0A
VCCIO0
J18
1
2
SDA
MCLK
3
4
SCL
SISPI
5
6
CDONE
SPISO
7
8
+2.5V
CSSPIN
9
10
10K
HEADER 5X2
MH1
MH2
MH3
MH4
ThruHole
ThruHole
ThruHole
MH6
MH7
MH8
MH9
ThruHole
ThruHole
ThruHole
3
CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
2
VCCIO0
NOTE : PLACE SPI FLASH IN THE TOP SIDE
IT SUPPORTS 2.5/3.3 V
R497
R498
2K
2K
R166
SPI FLASH
USB_SDA
1K
U14
USB_SCL
R412
0
5
2
0
SISPI
SDI
SDO
R413
0
6
MCLK
SCK
3
WP
SPI FLASH
1
7
CS
HOLD
CON2
M25PX16-VMW6TG
J19
TP18
1
VCCIO0
R80
680R
CDONE
U8E
D6
E3
GND
VCC
F4
E4
Green
GND
VCC
E5
GND
D10
C5
D5
GND
VCCAUX25VPP
D4
GND
G5
VCCGPLL
F5
GNDGPLL
C204
LIF-MD6000-6MG81I
100nF
16V
VCC_CORE
PLACE DECOUPLING CAPACITORS CLOSE TO THE U8 POWER PINS
C188
C185
C187
C186
10uF
0.1uF
0.1uF
0.1uF
MH5
ThruHole
ThruHole
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
MH10
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
ThruHole
ThruHole
Title
Title
Title
BANK0, Flash I/F
BANK0, Flash I/F
BANK0, Flash I/F
Size
Size
Size
Project
Project
Project
B
B
B
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
Date:
Date:
Date:
28-Mar-17
28-Mar-17
28-Mar-17
2
1
VCCIO0
C49
100nF
R123
R124
R125
10V
D
10K
10K
10K
R414
SPISO
{2,4,5,6}
C
VCC_CORE
0
R447
+2.5V
2
1
C70
C203
L12 120ohm 1.3A
100nF
2.2uF
16V
4V
B
A
Schematic Rev
Schematic Rev
Schematic Rev
1.0
1.0
1.0
Board Rev
Board Rev
Board Rev
1
1
1
Sheet
Sheet
Sheet
6
6
6
of
of
of
8
8
8
1
25
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