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Lattice LatticeECP2 User Manual

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LatticeECP2™ Standard Evaluation Board
User's Guide
May 2007
Revision: ebdug18_01.3

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Summary of Contents for Lattice LatticeECP2

  • Page 1 LatticeECP2™ Standard Evaluation Board User’s Guide May 2007 Revision: ebdug18_01.3...

  • Page 2: Electrical, Mechanical, And Environmental Specifications

    User’s Guide Introduction The LatticeECP2 Standard Evaluation Board is a complete, integrated design, featuring a LatticeECP2 FPGA and a variety of both application-specific and general-purpose peripheral interfaces. This board provides a convenient platform to evaluate, test, and debug user designs, including designs requiring PCI/PCI-X. This board includes the following features: •...

  • Page 3: Additional Resources

    LatticeECP2 pin J21 (this is the default position). When pin 1 of the oscilla- tor is aligned to pin 2 of the socket, the clock is routed to LatticeECP2 pin J21. When using a half size oscillator, align pin 1 of the oscillator to pin 1 of the socket to drive the primary clock, or align pin 1 of the oscillator to pin 5 of the socket to drive the PLL.
  • Page 4 Configuration/Programming Headers Two programming headers are provided on the evaluation board, providing access to the LatticeECP2 JTAG port and sysCONFIG™ port. The JTAG connector is a 1x10 header and the sysCONFIG connector is a 2x17 header. Both the JTAG and the sysCONFIG ports are also provided with loop-through connectors to allow for easy daisy chaining of multiple boards.
  • Page 5 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 3. sysCONFIG Header Pinout (J40) Function Function CCLK Ground BUSY / SISPI DI/D0 Vcc Bank8 D7 / DOUT INITN DONE PROGRAMN Ground Ground Ground Ground Ground Ground Ground Ground WRITEN CS1N...
  • Page 6 User’s Guide Default Jumpers Settings This table lists the default settings for all of the jumpers on the LatticeECP2 Standard Evaluation Board. For a com- plete description of each jumper refer to the next sections. Table 5. Default Jumper Settings...
  • Page 7 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 9. INITN Pin to JTAG Location Position Function Default 1 to 2 Connects INITN pin to the JTAG chain Open Disconnects INITN pin from the JTAG chain This jumper is normally not installed.
  • Page 8 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 16. Configuration Mode (J43) Configuration CFG[2], CFG[1], CFG[0], Mode 1 to 2 3 to 4 5 to 6 SPI (default) Jumper (0) Jumper (0) Jumper (0) Reserved Jumper (0) Jumper (0)

  • Page 9: Power Setup

    LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 20. Jumper Settings for SPI Emulation via J40 Location Position Notes Open Open 2 to 3 1 to 2 1 to 2 Open if driven by cable 3 to 4 Open if driven by cable...
  • Page 10 1 to 2 Connects 3.3V to VCCAUX The LatticeECP2 is divided into 10 banks of I/Os (see Table 24), and each of these banks has a separate and inde- pendent V Each bank supports voltages from 1.2V to 3.3V. However, because some banks, such as banks 4 and 5, which connect to PCI/PCI-X, require a fixed voltage, not all of the banks on this evaluation board are adjust-...
  • Page 11 2. Available on 50% of the I/Os in the Bank. PCI/PCI-X The LatticeECP2 Standard Evaluation Board is designed to be compatible with PCI (PCI SIG 2.2 specification) and PCI-X (Mode 1). All necessary signals required for 64-bit PCI/PCI-X operation are provided, as shown in Table 27 and Table 28.
  • Page 12 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 27. PCI Connections - Solder Side (Continued) Signal Name LatticeECP2 Pin sysIO Bank Note PCIX_ECC5 +3.3V PCIX_ECC3 +3.3VAUX TP13 PCI_RST_N +3.3V PCI_GNT_N PME# PCI_AD30 3.3V PCI_AD28 PCI_AD26 PCI_AD24 PCI_IDSEL +3.3V PCI_AD22...
  • Page 13 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 27. PCI Connections - Solder Side (Continued) Signal Name LatticeECP2 Pin sysIO Bank Note PCI_AD2 PCI_AD0 +3.3V PCI_REQ64_N PCI_CBE7_N PCI_CBE5_N +3.3V PAR64 PCI_AD62 PCI_AD60 PCI_AD58 PCI_AD56 PCI_AD54 +3.3V PCI_AD52 PCI_AD50 PCI_AD48...
  • Page 14 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 28. PCI Connections - Component Side Signal Name LatticeECP2 Pin sysIO Bank Notes -12V Decoupling cap PCI_TCK TP16, PD if master PCI_TDO TP17, J3, J13 PCI_INTB_N PCI_INTD_N PCI_PRSNT1_N PCIX_ECC4 PCI_PRSNT2_N PCIX_ECC2...
  • Page 15 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 28. PCI Connections - Component Side (Continued) Signal Name LatticeECP2 Pin sysIO Bank Notes PCI_AD12 AB10 PCI_AD10 AA11 PCI_M66EN PCI_AD8 AB11 PCI_AD7 +3.3V PCI_AD5 AB12 PCI_AD3 AA12 PCI_GND_57 PCI_AD1 AB13 +3.3V...
  • Page 16 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 28. PCI Connections - Component Side (Continued) Signal Name LatticeECP2 Pin sysIO Bank Notes Note: PD = pull-down resistor, PU = pull-up resistor, NC = no-connect, TP = test point. PCI/PCI-X Jumpers Table 29.
  • Page 17 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 34. PCI CLK Location Position Function Default Routes PCI_CLK to FPGA, only used if installing this board in a PCI or 1 to 2 PCI-X backplane. For signal integrity, also remove R27 and R30. D20 provides PCI clamping for this signal.

  • Page 18: Test Points

    The resistors can be used as termination or in combination to provide signal emulation (level shifting). For more information on signal emulation and signal types, please refer to Lattice techni- cal note number TN1102, LatticeECP2 sysIO Usage Guide, available on the Lattice web site at www.lattices- emi.com.

  • Page 19: Seven-Segment Display

    Note: During JTAG programming, the state of the DONE LED has no meaning. This is because the DONE pin, which drives the LED, is being controlled by the pin’s BSCAN cell. See Lattice technical note number TN1108, LatticeECP2 sysCONFIG Usage Guide, for more information on the dedicated programming pins.

  • Page 20: Lcd Connector

    LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 41. Seven-Segment Display Connections Segment Figure 4. Seven-Segment Display LCD Connector The LCD Connector has 18 pins, but only 16 are required for simple LCD panels. If using an OPTREX 51505 or equivalent, use pins 1-16, if using a LUMEX LCM-S02002DSR or equivalent, use pins 3-18.
  • Page 21 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Table 42. LCD Connector Signal FPGA Pin Anode (R34) — Cathode (GND) — VSS (GND) — VDD (5V) — VO (R35) — Anode (R34) — Cathode (GND) — Compact Flash The connector at J12 supports Type 1 and Type 2 Compact Flash cards. This connector supports PC Card Memory Mode, PC Card I/O Mode, and True IDE Mode.
  • Page 22 TN1108, LatticeECP2 sysCONFIG Usage Guide. SRAM Configuration The LatticeECP2 SRAM can be configured easily via the JTAG port. The LatticeECP2 device is SRAM-based, so it must remain powered to retain its configuration when programming just the SRAM. To program the SRAM, perform the following procedure: 1.
  • Page 23 Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the isp- DOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render the board inoperable.
  • Page 24 1. Install all three jumpers at J43, and the jumper at J44. This enables SPI mode by setting the CFG pins of the LatticeECP2, and it enables fast SPI reads. Check that J7 and J8 are properly set (see Table 6 and Table 7), and that J10 and J11 are open.

  • Page 25: Ordering Information

    Lattice Semiconductor User’s Guide 5. Press the SCAN button located on the toolbar. The LatticeECP2 device should be automatically detected. The resulting screen should be similar to Figure 5. 6. Double-click the device to open the device information dialog as shown in Figure 6. In the Device Options drop- down box, select SPI Flash Programming;...

  • Page 26: Revision History

    Replaced two instances of “U3-J21” with “LatticeECP2 pin J21” on page © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of...

  • Page 27: Appendix A. Schematics

    LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Appendix A. Schematics Figure 8. Block Diagram...
  • Page 28 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Figure 9. LCD, CF, RS-232, LEDs...
  • Page 29 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Figure 10. Prototyping Area...
  • Page 30 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Figure 11. 64-Bit PCI, PCI-X DQS Group DQS Group DQS Group DQS Group DQS Group DQS Group...
  • Page 31 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Figure 12. SI Testing DQS Group DQS Group DQS Group DQS Group...
  • Page 32 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Figure 13. JTAG and sysCONFIG...
  • Page 33 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Figure 14. FPGA Power...
  • Page 34 LatticeECP2 Standard Evaluation Board Lattice Semiconductor User’s Guide Figure 15. Power...
  • Page 35 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Lattice LS-E2-L-BASE-PC-N...

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