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5
D
VCC_DPHY
100E
C4
C6
R51
C41
C190
2.2uF
0.1uF
VCC_DPHY
4V
16V
B5
L11
2
1
D3
A5
120ohm 1.3A
C43
C189
2.2uF
0.1uF
VCC_DPHY
4V
16V
C
C3
L10
2
1
D7
120ohm 1.3A
C45
C178
2.2uF
0.1uF
16V
16V
C7
Note :
1) Match length within pair as well as other pairs within 0.2mm
B
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
4)Trace match P & N channels as well as individual pairs.
A
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0
4
U8D
CH5_DCK_TX_P
A1
VCCPLL_DPHY1
DPHY1_CKP
A2
CH5_DCK_TX_N
VCCPLL_DPHY0
DPHY1_CKN
B1
CH5_DATA0_TX_P
DPHY1_DP0
CH5_DATA0_TX_N
B2
DPHY1_DN0
A3
CH5_DATA1_TX_P
DPHY1_DP1
CH5_DATA1_TX_N
B3
DPHY1_DN1
C1
CH5_DATA2_TX_P
GNDPLL_DPHYX
DPHY1_DP2
CH5_DATA2_TX_N
C2
DPHY1_DN2
A4
CH5_DATA3_TX_P
DPHY1_DP3
CH5_DATA3_TX_N
B4
VCCA_DPHY1
DPHY1_DN3
VCCA_DPHY1
GNDA_DPHY1
CH4_DCK_TX_P
A8
DPHY0_CKP
A9
CH4_DCK_TX_N
DPHY0_CKN
CH4_DATA0_TX_P
B7
VCCA_DPHY0
DPHY0_DP0
A7
CH4_DATA0_TX_N
DPHY0_DN0
CH4_DATA1_TX_P
B8
DPHY0_DP1
B9
CH4_DATA1_TX_N
DPHY0_DN1
B6
CH4_DATA2_TX_P
DPHY0_DP2
A6
CH4_DATA2_TX_N
DPHY0_DN2
C8
CH4_DATA3_TX_P
DPHY0_DP3
CH4_DATA3_TX_N
C9
GNDA_DPHY0
DPHY0_DN3
LIF-MD6000-6MG81I
4
MIPI Block – MIPI Tx
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
U7
CH4_DCK_TX_P
1
CH4_DCK_P
CH4_DCK_TX_N
2
CH4_DCK_N
RESETN
3
GND
PWR_5-0V
CH4_DATA0_TX_P
4
CH4_DATA0_P
CH4_DATA0_TX_N
5
CH4_DATA0_N
6
GND
PWR_3-3V
CH4_DATA1_TX_P
7
CH4_DATA1_P
CH4_DATA1_TX_N
8
CH4_DATA1_N
9
GND
PWR_1-8V
CSSPIN
10
{2,5,6}
CSSPIN
SN
11
SCLK
12
GND
PWR_1-8V
CH4_DATA2_TX_P
13
CH4_DATA2_P
CH4_DATA2_TX_N
14
CH4_DATA2_N
15
GND
PWR_3-3V
CH4_DATA3_TX_P
16
CH4_DATA3_P
CH4_DATA3_TX_N
17
CH4_DATA3_N
12V
18
GND
PWR_5-0V
19
12V
20
12V
43
Shield3
Shield5
44
Shield4
Shield6
41
Shield1
Shield2
Hirose - FX12 - 40 Pos
U9
CH5_DCK_TX_P
1
CH5_DCK_P
TBD
CH5_DCK_TX_N
2
CH5_DCK_N
RESETN
3
GND
PWR_5-0V
CH5_DATA0_TX_P
4
CH5_DATA0_P
GND
CH5_DATA0_TX_N
5
CH5_DATA0_N
GND
6
GND
PWR_3-3V
CH5_DATA1_TX_P
7
CH5_DATA1_P
GND
CH5_DATA1_TX_N
8
CH5_DATA1_N
GND
9
GND
PWR_1-8V
CSSPIN
10
SN
MOSI
11
SCLK
MISO
12
GND
PWR_1-8V
CH5_DATA2_TX_P
13
CH5_DATA2_P
GND
CH5_DATA2_TX_N
14
CH5_DATA2_N
GND
15
GND
PWR_3-3V
CH5_DATA3_TX_P
16
CH5_DATA3_P
GND
CH5_DATA3_TX_N
17
CH5_DATA3_N
GND
12V
18
GND
PWR_5-0V
19
12V
SDA
20
12V
SCL
43
Shield3
Shield5
44
Shield4
Shield6
41
Shield1
Shield2
Hirose - FX12 - 40 Pos
3
CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
2
1
5V +3.3V +1.8V
12V
21
TBD
22
RESETN
0
R465
23
C155
C156
24
0.1uF
0.1uF
GND
25
GND
26
27
GND
28
GND
29
30
GPIO1
0
DNI
R418
MOSI
31
GPIO2
0
R419
MISO
DNI
32
33
GND
34
0
R420
GND
0
R421
35
36
GND
37
GND
38
39
0
R453
SDA
SDA
SDA
{6,7}
40
0
R454
SCL
SCL
{6,7}
SCL
45
46
42
5V +3.3V +1.8V
21
22
0
R466
RESETN
RESETN
23
24
25
26
27
12V
28
29
30
GPIO1
C159
C161
31
GPIO2
0.1uF
0.1uF
32
33
34
35
36
37
38
39
0
R455
SDA
40
0
R456
SCL
45
0
DNI
R481
XO3_SCL
{7}
46
0
R482
XO3_SDA
{7}
DNI
42
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
Title
Title
Title
MiPi Block - MIPI TX
MiPi Block - MIPI TX
MiPi Block - MIPI TX
Size
Size
Size
Project
Project
Project
B
B
B
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
Date:
Date:
Date:
28-Mar-17
28-Mar-17
28-Mar-17
2
1
5V
+3.3V
+1.8V
C157
C158
0.1uF
0.1uF
D
SISPI
{2,5,6}
SPISO
{2,5,6}
RPI1
{5}
RPI2
{5}
C
{5}
5V
+3.3V
+1.8V
C160
C162
0.1uF
0.1uF
B
A
Schematic Rev
Schematic Rev
Schematic Rev
1.0
1.0
1.0
Board Rev
Board Rev
Board Rev
1
1
1
Sheet
Sheet
Sheet
4
4
4
of
of
of
8
8
8
23
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