Lattice MachXO3D Breakout Board User Manual
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Lattice MachXO3D Breakout Board User Manual

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MachXO3D Breakout Board
User Guide
FPGA-UG-02084-0.90
July 2019

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Summary of Contents for Lattice MachXO3D Breakout Board

  • Page 1 MachXO3D Breakout Board User Guide FPGA-UG-02084-0.90 July 2019...
  • Page 2 The information provided in this document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at any time without notice.

  • Page 3: Table Of Contents

    Revision History .................................. 38 © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 4 Table B.1. MachXO3D Breakout Board Bill of Materials ..................... 35 © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 5: Acronyms In This Document

    Do Not Install © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 6: Introduction

    © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 7: Features

    MachXO3D Breakout Board User Guide 2. Features The MachXO3D Breakout Kit includes:  MachXO3D Breakout Board – The Board is a 3” × 3” form factor that features the following onboard components and circuits:  MachXO3D FPGA – Flash-based LCMXO3D-9400HC-5BG256C ...

  • Page 8: Figure 2.2. Machxo3D Breakout Board, Bottom Side

    Figure 2.2. MachXO3D Breakout Board, Bottom Side © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 9: Storage And Handling

    Touch a metal USB housing to equalize voltage potential between you and the Board. © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 10: Software Requirements

    Diamond or Diamond Programmer installation. © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 11: Machxo3D Device

    (FPGA-DS-02026). © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 12: Demonstration Design

    Communication between the Board and a PC through the USB connection cable requires installation of the FTDI Chip USB hardware drivers. Loading these drivers enables the computer to recognize and program the Board. Drivers can be loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a stand-alone package.

  • Page 13: Download Demo Designs

    © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 14: Programming A Demo Design With The Lattice Diamond Programmer

    Click the Program icon. When the process is completed, PASS is displayed in the Status column. © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 15: Machxo3D Breakout Board

    This section describes the features of the MachXO3D Breakout Board in detail. 7.1. Overview The MachXO3D Breakout Board is a complete development platform for the MachXO3D FPGA. The Board includes a prototyping area, a USB program/power port, an LED array, switches, and header landings with electrical connections to most of the FPGA programmable I/O, power, and configuration pins.

  • Page 16: Subsystems

    © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 17: Table 7.3. Expansion Header Pin Information For Bank 0 (J3)

    PT12A © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 18: Table 7.4. Expansion Header Pin Information For Bank 1 (J4)

    PR2D © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 19: Table 7.5. Expansion Header Pin Information For Bank 2 (J6)

    PB5B © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 20: Table 7.6. Expansion Header Pin Information For Bank 3/4/5 (J8)

    H7,J7 © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 21: Figure 7.2. J3/J4 Header Landing Callout

    Figure 7.3. J6/J8 Header Landing Callout © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 22: Machxo3D Fpga

    A7:TCK © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 23: Leds

    © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 24: Board Modifications

    7.3.2. Applying External Power The MachXO3D Breakout Board is powered by the circuit of Schematic showed on Sheet 3 of 8 based on the 5 V USB power source. You may disconnect this power source by removing the 0 Ω resistors: R35 (VCC_1.2 V) and R42 (VCC_3.3 V).

  • Page 25: Troubleshooting

    FPGA image. Resistor R23 should be re-installed if an external clock source is desired. 8.3. Determine the Source of a Pre-programmed Device If the MachXO3D Breakout Board has been reprogrammed, the original demo design can be restored. To restore the Board to the factory default, see the Download Demo Designs section for details on downloading and reprogramming the device.

  • Page 26: Ordering Information

    — © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 27: Schematics

    Figure A.1. Block Diagram © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 28: Figure A.2. Usb To Jtag Interface

    Figure A.2. USB to JTAG Interface © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 29: Figure A.3. Power Regulators

    Figure A.3. Power Regulators © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 30: Figure A.4. Bank0 I/O

    Figure A.4. Bank0 I/O © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 31: Figure A.5. Bank1 I/O

    Figure A.5. Bank1 I/O © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 32: Figure A.6. Bank2 I/O

    Figure A.6. Bank2 I/O © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 33: Figure A.7. Bank3, 4, 5 I/O

    Figure A.7. Bank3, 4, 5 I/O © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 34: Figure A.8. Power Decoupling And Leds

    Figure A.8. Power Decoupling and LEDs © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 35: Bill Of Materials

    NCP1117ST33T3G © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 36 7M-12.000MAAJ-T © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 37: References

    MachXO3D Programming and Configuration Usage Guide (FPGA-TN-02069) © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

  • Page 38: Revision History

    First preliminary release. © 2019 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
  • Page 39 www.latticesemi.com...

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