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CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
5
U8C
CH0_DATA0_P
F9
PB2A
F8
CH0_DATA0_N
PB2B
EXT_RST
G9
PB2C/MIPI_CLKT2_0
G8
CMOS_IO_5
PB2D/MIPI_CLKC2_0
CH0_DATA2_P
E9
PB6A/GR_PCLK2_0
E8
CH0_DATA2_N
PB6B
CH0_DATA1_P
H9
PB6C
H8
CH0_DATA1_N
PB6D
CMOS_IO_2
F7
PB12A/GPLLT2_0
D
E7
CMOS_IO_1
PB12B/GPLLC2_0
J9
CH0_DATA3_P
PB12C
CH0_DATA3_N
J8
PB12D
D9
CH0_DCK_P
PB16A/PCLKT2_0
CH0_DCK_N
D8
PB16B/PCLKC2_0
J7
CH2_DCK_P
PB16C/PCLKT2_1
CH2_DCK_N
H7
PB16D/PCLKC2_1
E6
VCCIO2
F6
VCCIO2
C51
100nF
LIF-MD6000-6MG81I
16V
U8B
CH1_DCK_P
G7
PB29A/PCLKT1_0
G6
CH1_DCK_N
PB29B/PCLKC1_0
J6
CH3_DCK_P
PB29C/PCLKT1_1
H6
CH3_DCK_N
PB29D/PCLKC1_1
D1
CH1_DATA1_P
C
PB34A/GR_PCLK1_0
CH1_DATA1_N
D2
PB34B
J5
CMOS_IO_3
PB34C/MIPI_CLKT1_0
CMOS_IO_4
H5
PB34D/MIPI_CLKC1_0
E1
CH1_DATA0_P
PB38A
CH1_DATA0_N
E2
PB38B
J4
CH1_DATA3_P
PB38C
CH1_DATA3_N
H4
PB38D
J3
CH1_DATA2_P
PB43C
CH1_DATA2_N
H3
PB43D
F3
VCCIO1
G4
VCCIO1
C58
C198
100nF
100nF
LIF-MD6000-6MG81I
16V
16V
NOTE : PLACE ALL THE TERMINATION
RESISTORS ON TOP SIDE AND CLOSE
TO THE U8
U12
CH0_DCK_P
1
B
CH0_DCK_P
CH0_DCK_N
2
CH0_DCK_N
3
GND
CH0_DATA0_P
4
CH0_DATA0_P
CH0_DATA0_N
5
CH0_DATA0_N
6
GND
CH0_DATA2_P
7
CH0_DATA2_P
CH0_DATA2_N
8
CH0_DATA2_N
9
GND
CSSPIN
10
{2,4,6}
CSSPIN
SN
11
SCLK
12V
12
PWR_12V
0
R461
13
{7}
SDA4
SDA1
0
R462
14
{7}
SCL4
SCL1
15
GND
CH2_DCK_P
16
CH2_DCK_P
CH2_DCK_N
17
CH2_DCK_N
18
GND
CMOS_IO_1
19
A
0
R471
CH2_DATA0_P
CMOS_IO_2
0
R472
20
CH2_DATA0_N
43
Shield3
44
Shield4
41
Shield1
Hirose - FX12 - 40 Pos
5
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
4
J29
CON3
Default short (J29.2,J29.3)
VCCIO2
VCCIO0
CMOS_IO_1
CMOS_IO_2
R56
CMOS_IO_3
DNI
RESETN
0
R450
4.7k
CMOS_IO_4
VCCIO2
C197
C200
100nF
10uF
Note :
1) Match length within pair as well as other pairs within 0.2mm
16V
2)Differential impedance should be 100 Ohms and 50 Ohms as a single ended signals
3)All the power rails should be capable of carrying 1A current
4)Trace match P & N channels as well as individual pairs.
VCCIO1
C199
10uF
12V
5V
+3.3V +1.8V
21
PWR_12-0V
22
0
R475
RESETN
RESETN
23
PWR_5-0V
24
CH0_DATA1_P
CH0_DATA1_P
CH0_DATA1_N
25
CH0_DATA1_N
26
PWR_3-3V
CH0_DATA3_P
27
CH0_DATA3_P
28
CH0_DATA3_N
CH0_DATA3_N
29
PWR_1-8V
30
GPIO3
MOSI
31
GPIO4
MISO
32
PWR_1-8V
33
GND
34
GND
35
PWR_3-3V
36
CMOS_IO_3
0
R469
CH2_DATA1_P
CMOS_IO_4
37
0
R470
CH2_DATA1_N
38
PWR_5-0V
39
0
R463
SDA2
SDA
40
0
R464
SCL
SCL2
45
Shield5
46
Shield6
42
Shield2
4
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
3
CH1_DCK_P
CH1_DCK_N
D6
R54
470E
blue
1
2
CH1_DATA0_P
CH1_DATA0_N
DNI
D7
R55
470E
blue
1
2
CH1_DATA2_P
D8
CH1_DATA2_N
R57
DNI
470E
blue
1
2
CSSPIN
DNI
D9
R59
470E
blue
1
2
12V
DNI
0
{7}
SDA3
0
{7}
SCL3
CH3_DCK_P
CH3_DCK_N
CMOS_IO_5
0
EXT_RST
0
VCCIO2
R445
SW4
4.7k
TL1015AF160QG
100E
R491
C184
1uF
EXTERNAL RESET
{7}
{7}
12V
5V
+3.3V
+1.8V
C167
C169
C168
C170
0.1uF
0.1uF
0.1uF
0.1uF
3
Bank 1, 2 – LVDS Rx
2
12V
5V
U11
1
21
CH1_DCK_P
PWR_12V
2
22
CH1_DCK_N
RESETN
3
23
GND
PWR_5-0V
4
24
CH1_DATA0_P
CH1_DATA1_P
5
25
CH1_DATA0_N
CH1_DATA1_N
6
26
GND
PWR_3-3V
7
27
CH1_DATA2_P
CH1_DATA3_P
8
28
CH1_DATA2_N
CH1_DATA3_N
9
29
GND
PWR_1-8V
10
30
SN
MOSI
11
31
SCLK
MISO
12
32
PWR_12_0V
PWR_1-8V
R457
13
33
SDA1
GND
R458
14
34
SCL1
GND
15
35
GND
PWR_3-3V
16
36
CH3_DCK_P
CH3_DATA1_P
17
37
CH3_DCK_N
CH3_DATA1_N
18
38
GND
PWR_5-0V
R467
19
39
CH3_DATA0_P
SDA
R468
20
40
CH3_DATA0_N
SCL
43
45
Shield3
Shield5
44
46
Shield4
Shield6
41
42
Shield1
Shield2
Hirose - FX12 - 40 Pos
GPIO3
GPIO4
EXT_RST
0
R446
R492
47K
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
Email: techsupport@Latticesemi.com
Title
Title
Title
BANK1,2 - LVDS RX
BANK1,2 - LVDS RX
BANK1,2 - LVDS RX
Size
Size
Size
Project
Project
Project
B
B
B
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
CrossLink_Master_Multi-Link_Board
Date:
Date:
Date:
28-Mar-17
28-Mar-17
28-Mar-17
2
1
+3.3V +1.8V
RESETN
0
R476
RESETN
{4}
CH1_DATA1_P
CH1_DATA1_N
D
CH1_DATA3_P
CH1_DATA3_N
GPIO3
GPIO4
0
R459
SDA1
{7}
0
R460
SCL1
{7}
12V
5V
+3.3V
+1.8V
C
C163
C165
C164
C166
0.1uF
0.1uF
0.1uF
0.1uF
0
DNI
R422
SISPI
{2,4,6}
0
R423
SPISO
{2,4,6}
DNI
0
R424
RPI1
{4}
0
R425
RPI2
{4}
J28
B
VCCIO1
1
CMOS_IO_1
2
CMOS_IO_2
3
CMOS_IO_3
4
CMOS_IO_4
5
6
CON6
A
Schematic Rev
Schematic Rev
Schematic Rev
1.0
1.0
1.0
Board Rev
Board Rev
Board Rev
1
1
1
Sheet
Sheet
Sheet
5
5
5
of
of
of
8
8
8
1
FPGA-EB-02018-1.0
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