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Lattice ORCA ORT42G5 Technical Note

Evaluating with with the high-speed serdes board
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April 2004
Introduction
Contained in this package is information that will assist you in evaluating and verifying your ORCA
designs using the Lattice High-Speed SERDES Board and the ORCAstra system bus control panel (available for
download from the Lattice web site at www.latticesemi.com/products/devtools/software/orcastra/index.cfm).
The Lattice High-Speed SERDES board supports a number of testing and evaluation setups for both the ORT42G5
and the ORSO42G5 . This document covers some common types of evaluation testing that can be performed on
the ORT42G5 device in raw (non-8b/10b) and 8b/10b modes. The tests include transmitter eye diagram measure-
ment, 8b/10b near-end loop-back and SERDES-only (non 8b/10b), 8b/10b and aligned 8b/10b far-end loop-back.
All of the described evaluation setups will use the ort42g5v10ceval.bit bitstream. This bitstream should be included
with the package that you have downloaded from the Lattice web site at www.latticesemi.com/products/dev-
tools/hardware/ort42g5-board/index.cfm. A unique ORCAstra macro is used to configure the device for each test.
PC and Evaluation Board Setup
This document assumes the ORCAstra application and bitstream programming software (ispVM
the user's PC. It also assumes the baseline board configuration listed below. (The user is also encouraged to
experiment with other configurations.)
• All jumpers should be in their default position and default programming in the ispPAC
described in the Evaluation Board User Manual. This will apply power in the recommended sequence and
provide 3.3V V
DDIO
®
• ispDOWNLOAD
tor on the board (J30). The pDS4102-DL2A is included with the Lattice High Speed SERDES Board. Alter-
nately, a HW-USB-1A ispDOWNLOAD cable can be used.)
• ORCAstra connected to the parallel or USB port on the PC and the ORCAstra Interface DB-25 or USB con-
nector on the board (J108).
• External differential clock connected to the External System Clock SMA connectors (J87/J88 and J84/J85).
• External power should be provided from the Molex cable and power module.
In addition, the following design-specific jumpers must be added. Note that references to "up" or "down" positions
on switches SW14-Cx are made with the assumption that the Lattice logo is to the right side when looking at the
board:
• Jumper pins 13 and 14 on J100 – This connects the global FPGA design's active low input reset to switch
SW14-C4. Make sure SW14-C4 remains in the "down" position to disable the reset for the duration of the
evaluation.
• Jumper pins 16 and 17 on J100 – This connects the input "clear_errors_n" signal to switch SW14-C3. Flip-
ping SW14-C3 from the "down" to the "up" position clears the "prbserror"(D9-1) and "pkterror"(D12-1) LEDS
described below.
• Jumper pins 19 and 20 on J100 – This connects the "farendlbad" input signal to switch SW14-C2. When
SW14-C2 is in the "down" position, channel AD is in far end loop-back mode.
• Jumper pins 22 and 23 on J100 – This connects the "farendlbac" input signal to switch SW14-C1. When
SW14-C1 is in the "down" position, channel AC is in far end loop-back mode.
• Jumper pins 2 and 3 on J100 – This connects the 2
design can be programmed to check 2
glow and remain lit anytime PRBS errors are detected. To clear D9-1, SW14-C3 needs to be flipped from
the "down" to the "up" position.
• Jumper pins 26 and 27 on J100 – This connects the 8b/10 packet error checker signal to the D12-1 LED.
The design can be programmed to check a predefined 8b/10 packet data (generated on the transmit side of
www.latticesemi.com
Evaluating the ORCA ORT42G5 with the
to all banks.
cable (pDS4102-DL2A) connected to the parallel port of the PC and to the ispVM connec-
7
-1 PRBS data on either of channels AC or AD in the FPGA. D9-1 will
High-Speed SERDES Board
7
-1 PRBS error checker signal to the D9-1 LED. The
1
Technical Note TN1069
®
ORT42G5
®
) are installed on
®
-POWR1208 as
tn1069_01

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Summary of Contents for Lattice ORCA ORT42G5

  • Page 1 • External power should be provided from the Molex cable and power module. In addition, the following design-specific jumpers must be added. Note that references to “up” or “down” positions on switches SW14-Cx are made with the assumption that the Lattice logo is to the right side when looking at the board: •...

  • Page 2: Recommended Reading

    Evaluating the ORCA ORT42G5 with the Lattice Semiconductor High-Speed SERDES Board AC and AD) on either of channels AC or AD in the FPGA. D12-1 will glow and remain lit anytime packet errors are detected. To clear D12-1, SW14-C3 needs to be flipped from the “down” to the “up” position.

  • Page 3: Ort42G5V10Ceval Bitstream

    Evaluating the ORCA ORT42G5 with the Lattice Semiconductor High-Speed SERDES Board ORT42G5V10CEVAL Bitstream The ort42g5v10ceval.bit design has been created as a base for all the described evaluation setups for the ORT42G5 device. As shown in Figure 3, the design takes advantage of the four SERDES channels available on the board.

  • Page 4: Transmit Eye Diagram Setup Requirements

    • Clock source capable of driving a CML input clock (77.76-155.52MHz) and SMA cables from the clock source to the Lattice High Speed SERDES Board and to the trigger input of the scope. (Note: The eye mea- surements could alternately be made using a Serial Data Analyzer. In that case no trigger connection is required.)

  • Page 5: Transmit Eye Diagram Test Procedures (8B/10B Data Eye)

    Evaluating the ORCA ORT42G5 with the Lattice Semiconductor High-Speed SERDES Board Transmit Eye Diagram Test Procedures (8b/10b Data Eye) 1. Connect the system as shown in Figure 4. The scope SMA cables should be connected to the HDOUTP_Bx and HDOUTN_Bx SMA connectors on the board.

  • Page 6: Near-End Loop-Back

    Evaluating the ORCA ORT42G5 with the Lattice Semiconductor High-Speed SERDES Board 3. Observe LED D12-1 (packet errors LED). If this LED is on, previous packet errors were seen. The LED needs to be cleared to see if it latches any additional errors. Move SW14-C3 to the “down” position, then to the “up”...

  • Page 7: Far-End Loop-Back

    Evaluating the ORCA ORT42G5 with the Lattice Semiconductor High-Speed SERDES Board 2. check the TESTEN check box for channel AD (or write Data=41, address =30034) in the ORCAstra GUI. This sets channel AD in internal loop-back while still enabling the data output to observe an eye on AD.

  • Page 8: Aligned 8B/10B Tests

    Evaluating the ORCA ORT42G5 with the Lattice Semiconductor High-Speed SERDES Board Figure 6. 8b/10b Data Path (ort42g5v10ceval.bit, Channel BC or BD) FPGA ASIC HDIN_Bx Rx 8b/10b Rx SERDES 32-Bit Data DOUTBx_FP RWCKBx HDOUT_Bx Tx 8b/10b Tx SERDES FIFO TSYSCLKBx TCK78B (Derived from REFCLK) Serial data is input through the CML buffer into the SERDES.

  • Page 9: Setup Requirements For Far-End Loop-Back Testing

    • 5V DC wall power supply. • Clock source capable of driving a CML input clock (77.76-155.52MHz) and SMA cables from the clock source to the Lattice High Speed SERDES Board. • ORCAstra GUI application and serdes_only_felp.fpm and 8b/10b_felp.fpm macros.

  • Page 10: Aligned 8B/10B Felb

    Evaluating the ORCA ORT42G5 with the Lattice Semiconductor High-Speed SERDES Board 6. Begin transmitting and analyzing data from the data source. Note: If at any point the REFCLK or data is stopped, the SERDES channel may need to be reset to reacquire data lock.

  • Page 11: Appendix A. Function Of The Bias Tee Network

    The FPSC 2.5/3.125G SERDES high speed outputs are designed to operate into 50Ω termination impedance biased at 1.5V or 1.8V DC. (This is the internal termination provided by Lattice 2.5/3.125G SERDES inputs and other vendor CML inputs.) Since most oscilloscopes and Digital Communications Analyzers (DCAs) have 50Ω...
  • Page 12 Not all bias tees are the same. There are a variety of bias tees designed for specific frequency ranges and DC cur- rent levels from several different vendors. Lattice uses a Picosecond Pulse Lab bias tee. More detailed character- ization and application documents are available from this vendor. See the references section at the end of this document.
  • Page 13 Evaluating the ORCA ORT42G5 with the Lattice Semiconductor High-Speed SERDES Board 2. Some newer test equipment provides adjustable bias voltage on the internal 50Ω input terminations. This equipment may be directly connected to the SERDES Tx output, as shown below.

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