Cisco EHWIC-4SHDSL-EA Configuration Manual page 33

Configuring Cisco Multimode G.SHDSL EFM/ATM in Cisco ISR G2
MAC110 Frame statistics registers
---------------------------------
Egress frame counters:
----------------------
Frame Count
Byte Count
Abort Count
Tx64 Bytes Packet Count0
Tx65_to_127 Bytes Packet Count9
Tx128_to_255 Bytes Packet Count0
Tx256_to_511
Tx512_to_1023 Bytes Packet Count 0
Tx1024_to_1518 Bytes Packet Count 0
TxUndersize Packet Count
TxOversize
Ingress frame counters:
--------------------------
Frame Count
Byte
Multicast Filt Drops
Multicast Frames
CRC Error Count
Congestion Drop Count 0
Oversize Drop Count
Pause Frame Count
Rx64 bytes Packet Count
Rx65_to_127 bytes Packet Count 8
Rx128_to_255 bytes Packet Count
Rx256_to_511 bytes Packet Count
Rx512_to_1023 bytes Packet Count
Rx1024_to_1518 bytes Packet Count 0
RxUndersize Packet Count
RxOversize
******* HWIC Host Registers at ECFEC000 *******
Status (0x00):
Card Present Low
Config (0x0000360E):
Hwic Reset
Hwic DDR Bus 50MHZ Enable
Hwic IRQ2 Type
Rx Queue Watermark Enable
Rx Int On Last
Generic Rx Enable
DDR Enable
Error Interrupt Enable (0x20D7E):
GDF Rx Resume Error Int
Rx Done Error Int
Hwic Int Frame Error Int
Tx Done Error Int
IRQ1 Int
Rx Overrun Int
Reg RW Timeout Int
Rx CRC Int
DMA Error Int
Management Interrupt Enable (0x0200):
Hwic Int Frame Mgmt Int
IRQ2 Int
IRQ1 Int
Network Interrupt Enable (0x00001C01):
GDF Ring 3 Interrupt Enables:
Rx Frame Drop Int
Generic Frame Rx Int
9
729
0
Bytes Packet Count 0
0
Packet Count 0
8
Count 648
8
8
0
0
0
0
0
Packet Count 0
0
0
0
0 Graceful Stop Tx Complete
0 Hwic Host Reset
0 Hwic EHWIC Mode Enable
Mgmt Hwic IRQ1 Type
0 Auto XOFF When Full
0 Graceful Stop Tx
1 Generic Tx Enable
1 Loopback
0
1 Card Present Change Int
0x00 Tx First Last Error Int
1 IRQ2 Int
1 Host Specific Error Int
1 DDR RxClk Missing Int
1 Reg RW Error Int
1 Rx Format Error Int
0
0x00
1
0 Graceful Stop Tx Int
0 Generic Frame Tx Int
0
Configuring Cisco Multimode G.SHDSL EFM/ATM in Cisco ISR G2
Troubleshooting Cisco G.SHDSL EFM/ATM
0
0
1
Err
0
0
1
0
0
1
0
0
1
1
1
0
0
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