Pin Configuration - Denon DN-X1600 Service Manual

PIN CONFIGURATION

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DB PACKAGE
SSOP-28
PCM1795 (IC101)
(TOP VIEW)
ZEROL 1
ZEROR 2
3
MSEL
LRCK 4
5
DATA
BCK 6
SCL 7
DGND 8
V
9
DD
10
MS
MDI 11
MC 12
MDO 13
RST 14
Table 1. TERMINAL FUNCTIONS
PCM1795 Pin Function
I/O
TERMINAL
— Analog ground (internal bias)
NAME NO.
— Analog ground (internal bias)
AGND1 19
— Analog ground (left channel DACFF)
AGND2 24
— Analog ground (right channel DACFF)
AGND3L 27
(1)
I Bit clock input
AGND3R 16
(2)
I Serial audio data input
BCK 6
— Digital ground
DATA 5
O Left channel analog current output+
DGND 8
O Left channel analog current output–
I L+ 25
OUT
O Right channel analog current output+
I L– 26
OUT
O Right channel analog current output–
I R+ 17
OUT
— Output current reference bias pin
I R– 18
OUT
I Left and right clock (f ) input
S
I 20
REF
(2)
I Mode control clock input
LRCK 4
(2)
I Mode control data input
MC 12
I/O Mode control readback data output
MDI 11
I/OI Mode control chip-select input
MDO 13
2 (2)
I I C/SPI select ; active low SPI select
MS 10
(2)
I Reset ; active low
MSEL 3
RST 14
PCM1795
2
C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a
(1) Schmitt-trigger input, 5-V tolerant.
(2) Schmitt-trigger input, 5-V tolerant.
(3) Schmitt-trigger input and output. 5-V tolerant input. In I
CMOS output.
(4) Schmitt-trigger input and output. 5-V tolerant input and CMOS output.
SLES248 – MAY 2009 ........................................................................................................................................................................................................
Product Folder Link(s):
Copyright © 2009, Texas Instruments Incorporated
TERMINAL
NAME NO.
SCK 7
V 1 23
CC
V 2L 28
CC
V 2R 15
CC
V L 22
COM
V R 21
COM
V 9
DD
ZEROL 1
ZEROR 2
PIN CONFIGURATION
DB PACKAGE
SSOP-28
(TOP VIEW)
V 2L
28
CC
27 AGND3L
ZEROL 1
I L-
26
OUT
ZEROR 2
I L+
25
OUT
MSEL 3
24 AGND2
LRCK 4
V 1
23
CC
DATA 5
V L
22
COM
BCK 6
V R
21
COM
7
SCL
I
20
REF
DGND 8
19 AGND1
V
9
DD
I R-
18
OUT
10
MS
I R+
17
OUT
MDI 11
16 AGND3R
MC 12
V 2R
15
CC
13
MDO
14
RST
Table 1. TERMINAL FUNCTIONS
DESCRIPTION
I/O
— Analog ground (internal bias)
— Analog ground (internal bias)
— Analog ground (left channel DACFF)
— Analog ground (right channel DACFF)
(1)
I Bit clock input
I Serial audio data input
— Digital ground
O Left channel analog current output+
O Left channel analog current output–
O Right channel analog current output+
O Right channel analog current output–
(2)
— Output current reference bias pin
I Left and right clock (f
I Mode control clock input
(3)
I Mode control data input
(4)
; active low
I/O Mode control readback data output
I/OI Mode control chip-select input
2 (2)
I I C/SPI select ; active low SPI select
(2)
I Reset ; active low
2
C mode, this pin becomes an open-drain 3-state output; otherwise, this pin is a
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PCM1795
Table 1. TERMINAL FUNCTIONS (continued)
Product Folder Link(s):
I/O
(2)
I System clock input
— Analog power supply, 5 V
— Analog power supply (left channel DACFF), 5 V
— Analog power supply (right channel DACFF), 5 V
— Left channel internal bias decoupling pin
— Right channel internal bias decoupling pin
— Digital power supply, 3.3 V
I/O Zero flag for left channel
I/O Zero flag for right channel
SLES248 – MAY 2009
V 2L
28
CC
27 AGND3L
I L-
26
OUT
I L+
25
OUT
24 AGND2
V 1
23
CC
V L
22
COM
V R
21
COM
I
20
REF
19
AGND1
I R-
18
OUT
I R+
17
OUT
16 AGND3R
V 2R
15
CC
DESCRIPTION
(2)
(2)
) input
S
(2)
(2)
(3)
(4)
; active low
7
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PCM1795
DESCRIPTION
(4)
(4)
84
SLES248 – MAY 2009
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7