Denon DN-X1600 Service Manual page 61

1.3 Block Diagram
R5S72630P200FP Block Diagram
SH-2A Floating-point
CPU core
Instruction
Cache
cache memory
controller
8 Kbytes
Internal LCD bus
(IL bus)
LCD
LCD I/F I/O
controller
(LCDC)
External bus I/O
External bus width
mode input
Pin function Clock pulse
controller I/O ports generator
(PFC) (CPG)
Port Port
General I/O EXTAL input
XTAL output
CKIO I/O
Clock mode input
User
Power-down On-chip RAM
debugging
mode (retention)
interface
control 16 Kbytes
(H-UDI)
Port
JTAG I/O
R5S72630P200FP Terminal Function
Pin No Pin name
1 PC10/RASU
2 /CASL
3 /RASL
4 VCC
5 DQMUU
6 VSS
7 PVSS
8 DQMUL
9 PVCC
10 DQMLU
11 /CS0
12 /RD
13 DQMLL, /WE0
14 PC3/CS3
15 PC2/CS2
16 VCC
17 PC0/A0/CS7
18 VSS
19 PVSS
unit (FPU)
Operand On-chip RAM
cache memory (high-speed)
8 Kbytes 64 Kbytes
Bus state USB2.0 host/ CD-ROM
controller function module decoder
(BSC) (USB) (ROM-DEC)
Port Port
USB bus I/O
USB clock input
Compare
Multi-function
Interrupt
match
timer pulse
controller
unit 2
timer
(INTC)
(MTU2)
(CMT)
Port Port
Timer pulse I/O
RES input
MRES input
MMI input
IRQ input
PINT input
IRQOUT output
Sampling AND/NAND
SD host
rate flash memory
interface
converter controller
(SDHI)
(SRC) (FLCTL)
Port Port
SD card I/F I/O Flash memory
I/F I/O
Figure 1.1 Block Diagram
I/O Pol
O
O N
O N
VCC
O
DGND
DGND
O
PVCC
O
O N
O N
O
O N
O N
VCC
O N
DGND
DGND
CPU instruction fetch bus (F bus)
CPU memory access bus (M bus)
User break
controller
UBCTRG output
(UBC)
Direct memory
Peripheral access
bus controller controller
(DMAC)
Serial
Watchdog Realtime
communication
timer clock
interface with FIFO
(WDT) (RTC)
(SCIF)
Port Port Port
RTC_X1 input Serial I/O
WDTOVF
RTC_X2 output
output
IEBusTM
D/A converter A/D converter
controller
(DAC) (ADC)
(IEB)
Port Port Port
Analog output Analog input IEBus input
ADTRG input
FADER CUE 4 OUTPUT
SDRAM(IC107) / Column Adress Strobe
SDRAM(IC107) / Row Adress Storbe
Rev. 2.00 Mar. 14, 2008 Page 11 of 1824
SDRAM(IC107) / Input/Output Mask
SDRAM(IC107) / Input/Output Mask
SDRAM(IC107) / Input/Output Mask
FLASH(IC103) / Chip Enable
FLASH(IC103) /Output Enable, ADSP / UHPI Select Signals
SDRAM(IC107) / Input/Output Mask 1, ADSP UHPI Select Signals
SDRAM(IC107) / Chip Select
FPGA / Panel scan signal
FPGA / Chip Select
61
Section 1 Overview
CPU bus
(C bus)
(I clock)
Internal CPU bus
(IC bus)
Internal bus
(I bus)
Internal DMA bus
(B clock)
(ID bus)
DREQ input
DACK output
TEND output
Peripheral bus (P clock)
Synchronous
2
I C bus
serial commnication
interface 3
unit
(IIC3)
(SSU)
Port Port
2
Serial I/O I C bus I/O
Controller Serial
area sound
network interface
(RCAN-TL1) (SSI)
Port Port
CAN bus I/O Serial I/O
Audio clock input
Function
REJ09B0290-0200