Denon DN-X1600 Service Manual page 77

Pin No BGA Location
86 F6
87 F7
88 F8
89 F9
90 F10
91 F11
92 F12
93 F13
94 F14
95 F15
96 F16
97 G1
98 G2
99 G3
100 G4
101 G5
102 G6
103 G7
104 G8
105 G9
106 G10
107 G11
108 G12
109 G13
110 G14
111 G15
112 G16
113 H1
114 H2
115 H3
116 H4
117 H5
118 H6
119 H7
120 H8
121 H9
122 H10
123 H11
124 H12
125 H13
126 H14
127 H15
128 H16
129 J1
130 J2
131 J3
132 J4
133 J5
134 J6
135 J7
136 J8
137 J9
138 J10
Pin name I/O
DGND DGND
SH_RW I
710RST O
SD0 I
SD1 I
ADDAT1 I
ADDAT2 I
NC NC
710HRDY. O
NC NC
_ASDWE I
SHA8 I
SHLRCK O
SHA3 I
SHA1 I
UNLCK_3 I
UNLCK_4 I
V1FPG VCCINT
DGND DGND
V1FPG VCCINT
DGND DGND
ADDAT3 I
ADDAT4 I
/UHPI_HRDY. I
/MIDICLK. O
DGND DGND
DSP_WAIT O
SHBCK O
V3FPG VCCO
SRC_OMCLK O
SHDB0.. IO
SHDATA1 I
SHDATA2 I
CS2 I
V1FPG VCCINT
DGND DGND
SRCD_1 I
SRCD_2 I
V3FPG VCCO
MIDICLK I
OUTD_3 O
OUTD_2 O
OUTPUT_BCK O
CPU_ACLK O
DAC_MCLK O
ADC_MCLK O
SHDB1.. IO
V3FPG VCCO
NC NC
SHRD I
DGND DGND
V1FPG VCCINT
SRCD_3 I
Pol
N Read/Write enable form CPU
N Reset for DSP
Panel switch dara
Panel switch dara
ADC data (PCM1804)
ADC data (PCM1804)
UHPI HRDY for CPU (Inverted)
N Write enable from DSP
10bits address bus (CPU)
USB Audio LR clock (CPU)
10bits address bus (CPU)
10bits address bus (CPU)
DIR PLL unlock signal (DIR9001)
DIR PLL unlock signal (DIR9001)
ADC data (PCM1804)
ADC data (PCM1804)
N UHPI HRDY from DSP
N MIDI clock (Inverted)
N Interrupt signal for DSP
USB Audio Bit clock (CPU)
SRC control (AK4125)
16bits data bus (CPU)
USB Audio data (CPU)
USB Audio data (CPU)
N Chip select (CPU)
Digital Audio data (AK4125)
Digital Audio data (AK4125)
MIDI clock from CPU
Selected Audio data
Selected Audio data
Bit clock for OUTPUT UNIT
Audio clock for CPU
Audio master clock for OUTPUT UINT
Audio master clock for INPUT UNIT
16bits data bus (CPU)
N Read enable (CPU)
Digital Audio data (AK4125)
77
Function