Denon DN-X1600 Service Manual page 78

Pin No BGA Location
139 J11
140 J12
141 J13
142 J14
143 J15
144 J16
145 K1
146 K2
147 K3
148 K4
149 K5
150 K6
151 K7
152 K8
153 K9
154 K10
155 K11
156 K12
157 K13
158 K14
159 K15
160 K16
161 L1
162 L2
163 L3
164 L4
165 L5
166 L6
167 L7
168 L8
169 L9
170 L10
171 L11
172 L12
173 L13
174 L14
175 L15
176 L16
177 M1
178 M2
179 M3
180 M4
181 M5
182 M6
183 M7
184 M8
185 M9
186 M10
187 M11
188 M12
189 M13
190 M14
191 M15
Pin name I/O
SRCD_4 I
FEMA12 I
FEMA11 I
OUTD_4 O
V3FPG VCCO
OUTD_1 O
NC NC
DGND DGND
AHCLK O
SHDB2.. IO
LRCKO_1. I
LRCKO_2. I
DGND DGND
V1FPG VCCINT
DGND DGND
V1FPG VCCINT
DSP_CE I
DSP_OE I
FEMA10 I
INPUT_LRCK O
OUTPUT_LRCK O
INPUT_BCK O
SHDB11.. IO
SHDB8.. IO
SHDB5.. IO
SHDB3.. IO
LRCKO_3. I
LRCKO_4. I
UOUT_1 I
UOUT_2 I
UOUT_3 I
UOUT_4 I
DGND DGND
V3FPG VCCAUX
FEMA9 I
FEMA6 I
DGND DGND
FEMA2 I
SHDB12.. IO
V3FPG VCCO
SHDB6.. IO
SHDB4.. IO
DGND DGND
V3FPG VCCAUX
BFRAME_2 I
BFRAME_3 I
V3FPG VCCO
FEMD14 IO
BFRAME_4 I
DGND DGND
FEMA8 I
FEMA5 I
FEMA3 I
Pol
Digital Audio data (AK4125)
13bits address bus (DSP)
13bits address bus (DSP)
Selected Audio data
Selected Audio data
Audio master clock for DSP
16bits data bus (CPU)
LR clock form DIR9001
LR clock form DIR9001
N Chip enable (DSP)
N Out enable (DSP)
13bits address bus (DSP)
LR clock for INPUT UNIT
LR clock for OUTPUT UNIT
Bit clock for INPUT UNIT
16bits data bus (CPU)
16bits data bus (CPU)
16bits data bus (CPU)
16bits data bus (CPU)
LR clock form DIR9001
LR clock form DIR9001
SPDIF user bit form DIR9001
SPDIF user bit form DIR9001
SPDIF user bit form DIR9001
SPDIF user bit form DIR9001
13bits address bus (DSP)
13bits address bus (DSP)
13bits address bus (DSP)
16bits data bus (CPU)
16bits data bus (CPU)
16bits data bus (CPU)
SPDIF user bit trigger (DIR9001)
SPDIF user bit trigger (DIR9001)
24bits data bus (DSP)
SPDIF user bit trigger (DIR9001)
13bits address bus (DSP)
13bits address bus (DSP)
13bits address bus (DSP)
78
Function