Denon DN-X1600 Service Manual page 79

Pin No BGA Location
192 M16
193 N1
194 N2
195 N3
196 N4
197 N5
198 N6
199 N7
200 N8
201 N9
202 N10
203 N11
204 N12
205 N13
206 N14
207 N15
208 N16
209 P1
210 P2
211 P3
212 P4
213 P5
214 P6
215 P7
216 P8
217 P9
218 P10
219 P11
220 P12
221 P13
222 P14
223 P15
224 P16
225 R1
226 R2
227 R3
228 R4
229 R5
230 R6
231 R7
232 R8
233 R9
234 R10
235 R11
236 R12
237 R13
238 R14
239 R15
240 R16
241 T1
242 T2
243 T3
244 T4
Pin name I/O
FEMA1 I
SHDB13.. IO
SHDB9.. IO
SHDB7.. IO
M1 PU
BFRAME_1 I
FEMD10 IO
FEMD11 IO
FEMD12 IO
FEMD13 IO
FEMD15 IO
FEMD16 IO
FEMD17 IO
FEMA7 I
FEMA4 I
V3FPG VCCO
FEMA0 I
SHDB14.. IO
SHDB10.. IO
DGND DGND
M0 PU
FEMD7 IO
FEMD8 IO
FEMD9 IO
710LRCK I
FEMD18 IO
FEMD19 IO
FEMD20 IO
FEMD21 IO
FEMD22 IO
DGND DGND
LCD_LED O
FEMD31 NC
SHDB15.. IO
M2 PU
FEMD5 IO
V3FPG VCCO
FEMD6 IO
DGND DGND
24.6M I
V3FPG VCCO
FEMD23 IO
DGND DGND
DOUT REV
V3FPG VCCO
NC NC
CCLK REV
NC NC
SUSPEND REV
DGND DGND
FEMD0 IO
FEMD1 IO
FEMD2 IO
Pol
13bits address bus (DSP)
16bits data bus (CPU)
16bits data bus (CPU)
16bits data bus (CPU)
Configuration reserve pin (Pull up)
SPDIF user bit trigger (DIR9001)
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
13bits address bus (DSP)
13bits address bus (DSP)
13bits address bus (DSP)
16bits data bus (CPU)
16bits data bus (CPU)
Configuration reserve pin (Pull up)
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
LR clock from DSP
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
LCD's LED control
16bits data bus (CPU)
Configuration reserve pin (Pull up)
24bits data bus (DSP)
24bits data bus (DSP)
24.576MHz master clock
24bits data bus (DSP)
Configuration reserve pin
Configuration reserve pin
Conservation of energy control (NC)
24bits data bus (DSP)
24bits data bus (DSP)
24bits data bus (DSP)
79
Function