Denon DN-X1600 Service Manual page 63

Pin No Pin name
73 PE12/RXD3
74 VCC
75 /WAIT
76 VSS
77 PVSS
78 RTC_X1
79 RTC_X2
80 PVCC
81 PE13/TXD3
82 CS1
83 PE15
84 PVSS
85 PB8
86 PB9
87 PB10
88 PB11
89 VCC
90 MD
91 VSS
92 PVSS
93 USB_X1
94 USB_X2
95 PVCC
96 MD_CLK1
97 MD_CLK0
98 USBDPVSS
99 USBDPVCC
100 DM
101 DP
102 VBUS
103 USBAVCC
104 USBAVSS
105 REFRIN
106 USBAPVSS
107 USBAPVCC
108 USBDVCC
109 USBDVSS
110 AN0
111 AN1
112 AN2
113 AN3
114 AVCC
115 AN4
116 AVREF
117 AN5
118 AN6/DA0
119 AN7/DA1
120 AVSS
121 PVSS
122 /WDTOVF
123 PVCC
124 SSIDATA3
125 SSIWS3
I/O Pol
O FADER PLAY 3 Output
VCC
I N ADSP HRDY
DGND
DGND
DGND
NC
PVCC
O LCD Serial Control DATA @X1700 / NC @X1600
O FPGA Configration
I FPGA Configration
DGND
I CPU-DSP FLAG(backup)
I USB Control
O USB Control
O USB Control
VCC
I MODE Select （1:32bit/0:16bit)
DGND
DGND
I X'tal Port for USB(48MHz)
O X'tal Port for USB(48MHz)
PVCC
DGND
DGND
DGND
USBDPVCC
I/O USB(B) D- Terminal
I/O USB(B) D+ Terminal
I VBUS Detected Terminal
USBAVCC
DGND
I Reference Input (USB)
DGND
USBAPVCC
USBDVCC
DGND
I CH FADER 1/2 INPUT
I CH FADER 3/4 INPUT
I X FADER INPUT
I CH1 VR INPUT
AVCC
I CH2 VR INPUT
I Transrated Reference Voltage Input
I CH3 VR INPUT
I CH4 VR INPUT
O LCD Backlight LED MOD. @X1700 / NC @X1600
DGND
DGND
O FADER PLAY1 OUTPUT
PVCC
O FPGA / USB Audio data
I FPGA / USB Audio LR clock
Function
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