Master Mode; Slave Mode; High-Pass Filter And Dc Offset Calibration; Figure 10.Master Mode Clocking - Cirrus Logic CS4265 Manual

In both Master and Slave Modes, the external MCLK must be divided down based on the MCLK/LRCK
ratio to achieve a post-divider MCLK/LRCK ratio of 256x for SSM, 128x for DSM, or 64x for QSM.
lists the appropriate dividers.
MCLK/LRCK Ratio
4.2.2

Master Mode

As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in
4.2.3

Slave Mode

In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x, 48x or 32x Fs, depending on the desired speed mode. Refer to
tios.
SCLK/LRCK Ratio
4.3

High-Pass Filter and DC Offset Calibration

When using operational amplifiers in the input circuitry driving the CS4265, a small DC offset may be driven
into the A/D converter. The CS4265 includes a high-pass filter after the decimator to remove any DC offset
DS657F3
-
64x
-
96x
-
128x
-
192x
÷1
256x
÷1.5
384x
÷2
512x
÷3
768x
÷4
1024x
Mode SSM

Table 3. MCLK Dividers

MCLK Freq Bits
000
÷1
÷1.5 001
MCLK ÷2 010
011
÷3
÷4
100
Figure 10. Master Mode Clocking
Single-Speed
32x, 48x, 64x, 128x

Table 4. Slave Mode Serial Bit Clock Ratios

MCLK Dividers
-
- ÷1.5
÷1
÷1.5
÷2
÷3
÷4
-
-
DSM QSM
Figure
÷256 00
÷128 01 LRCK
÷64 10
FM Bits
÷4 00
÷2 01 SCLK
÷1
10
Double-Speed
32x, 48x, 64x
CS4265
Table 3
÷1
÷2
÷3
÷4
-
-
-
-
10.
Table 4 for required clock ra-
Quad-Speed
32x, 48x, 64x
25