Mute Adc (Bit 2); Adc High-Pass Filter Freeze (Bit 1); Master / Slave Mode (Bit 0); Mclk Frequency - Address 05H - Cirrus Logic CS4265 Manual

ADC_DIF
0
1
6.4.3

Mute ADC (Bit 2)

Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
6.4.4

ADC High-Pass Filter Freeze (Bit 1)

Function:
When this bit is set, the internal high-pass filter is disabled. The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See
page 25.
6.4.5

Master / Slave Mode (Bit 0)

Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
6.5

MCLK Frequency - Address 05h

7 6
MCLK
Reserved
Freq2
6.5.1

Master Clock Dividers (Bits 6:4)

Function:
Sets the frequency of the supplied MCLK signal. See
DS657F3
Description
Left-Justified, up to 24-bit data (default)
I²S, up to 24-bit data

Table 10. ADC Digital Interface Formats

5
MCLK MCLK
Freq1 Freq0
MCLK Divider MCLK Freq2
÷ 1
÷ 1.5
÷ 2
÷ 3
÷ 4
Reserved
Reserved

Table 11. MCLK Frequency

"High-Pass Filter and DC Offset Calibration" on
4 3
Reserved
Table 11
MCLK Freq1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
Format Figure
0 5
1 6
2 1
Reserved Reserved
for the appropriate settings.
MCLK Freq0
0
1
0
1
0
1
x
CS4265
0
Reserved
39