Switching Characteristics; Figure 1. Serial Audio Port Master Mode Timing; Figure 2. Serial Audio Port Slave Mode Timing - Cirrus Logic CDB42528 Manual

SWITCHING CHARACTERISTICS

VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C
Parameters
RST pin Low Pulse Width
PLL Clock Recovery Sample Rate Range
RMCK output jitter
RMCK output duty cycle
OMCK Frequency
OMCK Duty Cycle
CX_SCLK, SAI_SCLK Duty Cycle
CX_LRCK, SAI_LRCK Duty Cycle
Master Mode
RMCK to CX_SCLK, SAI_SCLK active edge delay
RMCK to CX_LRCK, SAI_LRCK delay
Slave Mode
CX_SCLK, SAI_SCLK Falling Edge to CX_SDOUT,
SAI_SDOUT Output Valid
CX_LRCK, SAI_LRCK Edge to MSB Valid
CX_SDIN Setup Time Before CX_SCLK Rising Edge
CX_SDIN Hold Time After CX_SCLK Rising Edge
CX_SCLK, SAI_SCLK High Time
CX_SCLK, SAI_SCLK Low Time
CX_SCLK, SAI_SCLK falling to CX_LRCK,
SAI_LRCK Edge
Notes: 12. After powering up the CS42528, RST should be held low after the power supplies and clocks are settled.
13. See Table 1 on page 26 for suggested OMCK frequencies
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in "Clock Control (address 06h)" on page 53 is set to Multiply by 2.
CX_SCLK
SAI_SCLK
(output)
CX_LRCK
SAI_LRCK
(output)
t smd
RMCK

Figure 1. Serial Audio Port Master Mode Timing

12
(For CQZ, T
Symbol
(Note 12)
(Note 14)
(Note 15)
(Note 13)
(Note 13)
t
smd
t
lmd
t
dpd
t
lrpd
t
ds
t
dh
t
sckh
t
sckl
t
lrck
CX_LRCK
SAI_LRCK
(input)
CX_SCLK
SAI_SCLK
(input)
CX_SDINx
t
lmd
CX_SDOUT
SAI_SDOUT
= -10 to +70° C; For DQZ, T
A
Min Typ
1 -
30 -
- 200
45 50
1.024 -
40 50
45 50
45 50
0 -
0 -
-
-
10 -
30 -
20 -
20 -
-25 -
t
lrck
t
t
lrpd
ds

Figure 2. Serial Audio Port Slave Mode Timing

CS42528
= -40 to +85° C;
A
= 30 pF)
L
Max Units
- ms
200 kHz
- ps RMS
55 %
25.600 MHz
60 %
55 %
55 %
15 ns
15 ns
50 ns
20 ns
- ns
- ns
- ns
- ns
+25 ns
t
t
sckh sckl
t
dh t dpd
MSB MSB-1
DS586PP5