Analog Input Multiplexer, Pga, And Mic Gain; Input Connections; Pseudo-Differential Input; Figure 11.Analog Input Architecture - Cirrus Logic CS4265 Manual

4.4

Analog Input Multiplexer, PGA, and Mic Gain

The CS4265 contains a stereo 2-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer is able to select either a line-level input source, or a mic-level input source, and
route it to the PGA. The mic-level input passes through a +32 dB gain stage prior to the input multiplexer,
allowing it to be used for microphone-level signals without the need for any external gain. The PGA stage
provides 12 dB of gain or attenuation in 0.5 dB steps.
plexer, PGA, and mic gain stages.
The "Analog Input Selection (Bit 0)" on page 41
tiplexer and mic gain.
Address 08h" on page 40
level input is selected by the input multiplexer, and the PGA is set to 0 dB.
4.5

Input Connections

The analog modulator samples the i n put at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject sig-
nals within the stopband of the filter. However, there is no rejection for input signals

(n 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capac-
itors which have a lar ge voltage coefficient (such as ge neral-purpose ceramics) must be avoided since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.5.1

Pseudo-Differential Input

The CS4265 implements a pseudo-differential input stage. The SGND input is intended to be used as a
pseudo-differential reference signal. This feature allows for common mode noise rejection with single-
ended signals.
ferential input stage. The Typical Connection Diagram shows the recommended pseudo-differential input
DS657F3
AINA
MICIN1
+32 dB
AINB
MICIN2
+32 dB
Figure 11. Analog Input Architecture
"Channel B PGA Control - Address 07h" on page 40
outline the register settings necessary to control the PGA. By default, the line-
Figure 12 shows a basic diagram outlining the internal implementation of the pseudo-dif-
Figure 11 shows the architecture of the input multi-
Out to ADC
MUX PGA
Channel A
Channel A
PGA Gain Bits
Analog Input
Selection Bits
Channel B
PGA Gain Bits
Out to ADC
MUX PGA
Channel B
outlines the bit settings necessary to control the input mul-
CS4265
and "Channel A PGA Control -
which are
27