Invert Dac Output (Bit 5); Status - Address 0Dh; E To F C-Buffer Transfer; Clock Error (Bit 3) - Cirrus Logic CS4265 Manual

ple rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel. See
DACSoft
0
0
1
1

6.12.2 Invert DAC Output (Bit 5)

Function:
When this bit is set, the output of the DAC is inverted.
6.13

Status - Address 0Dh

7 6
Reserved Reserved
For all bits in this register, a '1' means the associated condition has occurred at least once since the register
was last read. A '0' means the associated condition has NOT occurred since the last reading of the register.
Status bits that are masked off in the associated mask register will always be '0' in this register. This register
defaults to 00h.

6.13.1 E to F C-Buffer Transfer

Function:
Indicates the completion of an E to F C-buffer transfer. See
page 53 for more information.

6.13.2 Clock Error (Bit 3)

Function:
Indicates the occurrence of a clock error condition.

6.13.3 ADC Overflow (Bit 1)

Function:
Indicates the occurrence of an ADC overflow condition.

6.13.4 ADC Underflow (Bit 0)

Function:
Indicates the occurrence of an ADC underflow condition.
DS657F3
DACZeroCross
0 Changes to affect immediately
1 Zero Cross enabled
0 Soft Ramp enabled
1 Soft Ramp and Zero Cross enabled (default)

Table 17. DAC Soft Cross or Zero Cross Mode Selection

5 4
Reserved EFTC
Table 17.
Mode
3 2
ClkErr Reserved
"Channel Status Buffer Management" on
CS4265
1 0
ADCOvfl ADCUndrfl
43