Pll Circuits; Power Supply Circuits - Icom IC-F2610 Service Manual

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL circuit con-
sists of the PLL IC, charge pump, loop filter and reference
oscillator and employs a pulse swallow counter.
Oscillated signals from the VCO via the buffer amplifiers
(Q19, Q18) are prescaled in the PLL IC (IC12, pin 11) based
on the divided ratio (N-data). The PLL IC detects the out-of-
step phase using the reference frequency and outputs it
from pin 6 (IC12). The output signal is passed through the
charge pump (Q30–Q33) and loop filters (R154/C181,
R153/C179), and is then applied to the VCO circuit as the
lock voltage.
The accelerator switch (IC13) selects the effective loop filter
to accelerate the PLL lock up speed.
The lock voltage is also used for the receiver tunable band-
pass filters to match the filter's center frequency to the
desired receive frequency. The lock voltage is amplified at
the buffer amplifier (Q29) and is then applied to the band-
pass filters (D7–D11, D514) as center frequency control sig-
nal.
4-3-2 VCO CIRCUIT (MAIN UNIT)
The VCO circuit contains a separate Rx VCO (Q21, D19,
D20) and Tx VCO (Q23, D21, D22, D46). The oscillated sig-
nal is amplified at the buffer amplifiers (Q19, Q20) and is
then applied to the T/R switches (D17, D18). Then the
receive 1st LO (Rx) signal is applied to the 1st mixer (Q2) via
the LO amplifier (Q3) and the transmit (Tx) signal to the dri-
ver (Q17).
A portion of the signal from the buffer amplifier (Q19) is fed
back to the PLL IC (IC12, pin 11) via the another buffer
amplifier (Q18) as the comparison signal.
• PLL CIRCUIT
Loop
filter
Charge
pump
X501
12.6 MHz
Rx VCO
Q21,
D19, D20
Buffer
Q19
Tx VCO
Q23,
D21, D22, D46
IC12 (PLL IC)
Phase Programmable
6
detector counter
20 Programmable
divider
4-4 POWER SUPPLY CIRCUIT
VOLTAGE LINE
LINE
HV The voltage from the external power connector.
Same voltage as the HV line passed through the
VCC power control circuit (Q12, Q14) controlled by
PWON signal from the CPU (IC20, pin 77).
Common 5 V converted from the HV line at the
CPU5V 5V regulator circuit (IC17). This voltage is sup-
plied to the CPU regardless of the power switch.
Common 5 V converted from the VCC line at the
+5V +5V regulator circuit (Q42, Q43, D30) using the
CPU5V line voltage as the reference.
Common 8 V converted from the VCC line at the
+8V
+8V regulator circuit (IC16).
Receive 8 V converted from the VCC line at the
R8V regulator circuit (Q36, Q37, D27) using the
R8V
+8V line voltage as the reference and controlled
by VRX signal from the CPU (IC20, pin 76).
Transmit 8 V converted from the VCC line at the
T8V regulator circuit (Q40, Q41, D29) using the
T8V
+8V line voltage as the reference and controlled
by VTX signal from the the CPU (IC20, pin 75).
Transmit 8 V converted from the VCC line at the
MT8V regulator circuit (Q38, D28) using the +8V
MT8V
line voltage as the reference and controlled by
TMUT signal from the the CPU (IC20, pin 62).
Common 12 V converted from the +12V regula-
tor circuit (IC506, Q508, Q509) using the VCC
FVPP
line. The circuit is controlled by the FVPC line
from the CPU (IC20, pin 10).
Common 18 V converted from the +18V DC/DC
convertor circuit (IC18, Q44, D31–D33) using
+18V the +8V line. The output voltage is applied to the
buffer amplifier (Q29) and loop filter (IC13,
Q30–Q33).
Buffer
Q20
Buffer
Q18
Prescaler
Shift register
4 - 4
DESCRIPTION
D18
to 1st mixer circuit
D17
to transmitter circuit
11
17
PSTB
18
PCK
19
PDA