Veikong VFD500 Series Operation Manual page 69

VFD500 high performance vector control frequency inverter user manual
P23.24 fault reset
P23.25 fault source for auto reset
P23.26 Fault auto Reset times
Numberic output Action at
P23.27
fault reset
Interval time of fault auto
P23.28
reset
Fault auto reset times
P23.29
clearing time
continuing Running
P23.30 frequency selection when
trip
abnormal back-up
P23.31
frequency
Define as per bit:
bit0-undervoltage;bit1- inverter overload
bit2-inverter overheat ;bit3-motor overload
bit4-motor overheat;bit5-user'fault 1
bit6- user'fault 2; bit7～15 reserved
Define as per bit:
bit0-overcurrent during
acceleration;bit1-overcurrent during deceleration
bit2-overcurrent during constant speed;bit3-over
voltage during acceleration
bit4-overvoltage during
deceleratoin;bit5-overvoltage during
bit6-inverter undervoltage;bit7-input phase loss
bit8-inverter overload;bit9-inverter overheat
bit10-motor overload;bit11-motor overheat
bit12-user'fault 1;bit13-user'fault 2
bit14-Reserved;bit15-Reserved
0～99
0:disabled
1:enabled
0.1s～300.0s
0.1s～3600.0s
0：run at current frequency
1：run at setted frequency
2：run at upper limite frequency
3：run at lower limit frequency
4：run at abnormal back-up frequency
0.0%～100.0%(maximum frequency )
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Chapter 5 function code table
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0
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0
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0
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0
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0.5s
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10.0s
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0
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5.0%