Veikong VFD500 Series Operation Manual page 51

VFD500 high performance vector control frequency inverter user manual
VDO2(virtual DO2) output
P07.10
Terminal function
P07.11 output logic negative
P07.12 DO1 effective delay time
P07.13 DO1 ineffective delay time
P07.14 DO2 effective delay time
P07.15 DO2 ineffective delay time
Relay 1 effective delay
P07.16
time
Relay 1 ineffective delay
P07.17
time
Relay 2 effective delay
P07.18
time
Relay 2 ineffective delay
P07.19
time
31:Single running time arrival
32:Variable selector unit 1 output
33:Variable selector unit 2 output
34:Variable selector unit 3 output
35:Variable selector unit 4 output
36:Logic unit 1 output
37:Logic unit 2 output
38:Logic unit 3 output
39:Logic unit 4 output
40:delaying unit 1 output
41:delaying unit 2 output
42: delaying unit 3 output
43: delaying unit 4 output
44: delaying unit 5 output
45: delaying unit 6 output
Define as per bit O:off;1:on(negative)
Bit0:DO1
Bit1:DO2
Bit2:Relay 1
Bit3: Relay 2
Bit4: DO3;Bit5: DO4 Bit6: DO5; Bit7: DO6
Bit8: VDO1;Bit9: VDO2
Notice:posive logic equivalent to Normal open
point
And negative logic equivalent to Normal close
point
0.000s～30.000s
0.000s～30.000s
0.000s～30.000s
0.000s～30.000s
0.000s～30.000s
0.000s～30.000s
0.000s～30.000s
0.000s～30.000s
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Chapter 5 function code table
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