Figure 4 Pmc Biserial-Iii-Hw2 Async Block Diagram - Dynamic Engineering PMC-BiSerial-III HW2 User Manual

Each asynchronous interface uses either programmable PLL clock B or a fixed 5 MHz
as its 16x reference frequency with data in and out using two of the four I/O lines of the
channel block. Two DPRs are used for each asynchronous interface, one each for
transmit and receive circular buffers that have independently specified start and stop
addresses.
FIGURE 4 PMC BISERIAL-III-HW2 ASYNC BLOCK DIAGRAM
The two asynchronous interfaces in a channel block are independently configurable
and each have separate receive and transmit interrupts.
All the data I/O lines on the HW2 are programmable to be register controlled or state-
machine controlled. Any or all of the bits can be used as a parallel port instead of being
dedicated to a specific I/O protocol. Thirty-four differential I/O are provided at the front
bezel (32 of the 34 at Pn4) for the serial signals. The drivers and receivers conform to
the RS-485 specification (exceeds RS-422 specification). The RS-485 input signals are
selectively terminated with 100Ω. The termination resistors are in two-element
Embedded Solutions
Page 9 of 50