Figure 2 Pmc Biserial-Iii-Hw2 P2P Block Diagram - Dynamic Engineering PMC-BiSerial-III HW2 User Manual

The standard configuration shown in Figure 1 makes use of two external (to the Xilinx)
FIFOs. The FIFOs can be as large as 128K deep x 32 bits wide. Some designs do not
require so much memory, and are more efficiently implemented using the Xilinx internal
memory.
FIGURE 2 PMC BISERIAL-III-HW2 P2P BLOCK DIAGRAM
The HW2 implementation has 32 – Dual Port RAM (DPR) blocks implemented using
the Xilinx internal block RAM. Each channel has one or more associated DPRs
depending on which mode is active. Each DPR is configured to have a 32-bit port on
the PCI side, and a 16-bit port on the I/O side.
The lower eight channels are configured with the point-to-point interface that was used
on the HW1. In this mode when operating in the bidirectional mode the DPR is split in
half to provide both transmit, and receive buffers. In the unidirectional mode the full
DPR can be used for transmit or receive data.
Embedded Solutions
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